ACM Transactions on Design of Automated Electronic Systems

2005

Editorial
by: Nikil D. Dutt v. 10 i. 1 p. 1 - 2
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
by: Jason Cong, Hui Huang, Xin Yuan v. 10 i. 1 p. 3 - 23
Bipartitioning and encoding in low-power pipelined circuits
by: Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai v. 10 i. 1 p. 24 - 32
A scheduling algorithm for optimization and early planning in high-level synthesis
by: Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh v. 10 i. 1 p. 33 - 57
Combinatorial techniques for mixed-size placement
by: Saurabh N. Adya, Igor L. Markov v. 10 i. 1 p. 58 - 90
RL-huffman encoding for test compression and power reduction in scan applications
by: Mehrdad Nourani, Mohammad H. Tehranipour v. 10 i. 1 p. 91 - 115
A 4-geometry maze router and its application on multiterminal nets
by: Gene Eu Jan, Ki-Yin Chang, Su Gao, Ian Parberry v. 10 i. 1 p. 116 - 135
Algorithmic aspects of hardware/software partitioning
by: Péter Arató, Zoltán Ádám Mann, András Orbán v. 10 i. 1 p. 136 - 156
A unified method for phase shifter computation
by: Dimitrios Kagaris v. 10 i. 1 p. 157 - 167
An efficient algorithm for finding the minimal-area FPGA technology mapping
by: Chi-Chou Kao, Yen-Tai Lai v. 10 i. 1 p. 168 - 186
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques
by: Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria v. 10 i. 2 p. 187 - 204
Synthesis of skewed logic circuits
by: Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy v. 10 i. 2 p. 205 - 228
Optimizing instruction TLB energy using software and hardware techniques
by: Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen v. 10 i. 2 p. 229 - 257
Efficient techniques for transition testing
by: Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran v. 10 i. 2 p. 258 - 278
A detailed power model for field-programmable gate arrays
by: Kara K. W. Poon, Steven J. E. Wilton, Andy Yan v. 10 i. 2 p. 279 - 302
Optimized wafer-probe and assembled package test design for analog circuits
by: Soumendu Bhattacharya, Abhijit Chatterjee v. 10 i. 2 p. 303 - 329
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
by: Saraju P. Mohanty, N. Ranganathan v. 10 i. 2 p. 330 - 353
Voltage scheduling under unpredictabilities: a risk management paradigm
by: Azadeh Davoodi, Ankur Srivastava v. 10 i. 2 p. 354 - 368
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
by: Zhong Wang, Xiaobo Sharon Hu v. 10 i. 2 p. 369 - 388
Large-scale circuit placement
by: Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan v. 10 i. 2 p. 389 - 430

2004

Formal hardware specification languages for protocol compliance verification
by: Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee v. 9 i. 1 p. 1 - 32
Power minimization algorithms for LUT-based FPGA technology mapping
by: Hao Li, Srinivas Katkoori, Wai-Kei Mak v. 9 i. 1 p. 33 - 51
Fast memory bank assignment for fixed-point digital signal processors
by: Jeonghun Cho, Yunheung Paek, David B. Whalley v. 9 i. 1 p. 52 - 74
Manhattan-diagonal routing in channels and switchboxes
by: Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya v. 9 i. 1 p. 75 - 104
A BNF-based automatic test program generator for compatible microprocessor verification
by: Lieh-Ming Wu, Kuochen Wang, Chuang-Yi Chiu v. 9 i. 1 p. 105 - 132
Storage requirement estimation for optimized design of data intensive applications
by: Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas v. 9 i. 2 p. 133 - 158
IDDX-based test methods: A survey
by: Sagar S. Sabade, D. M. H. Walker v. 9 i. 2 p. 159 - 198
Stairway compaction using corner block list and its applications with rectilinear blocks
by: Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu v. 9 i. 2 p. 199 - 211
Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications
by: Praveen K. Murthy, Shuvra S. Bhattacharyya v. 9 i. 2 p. 212 - 237
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications
by: Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri v. 9 i. 2 p. 238 - 271
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints
by: Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi v. 9 i. 3 p. 273 - 289
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
by: Kevin M. Lepak, Min Xu, Jun Chen, Lei He v. 9 i. 3 p. 290 - 309
Annealing placement by thermodynamic combinatorial optimization
by: Juan de Vicente, Juan Lanchares, Román Hermida v. 9 i. 3 p. 310 - 332
An adaptive cryptographic engine for internet protocol security architectures
by: Andreas Dandalis, Viktor K. Prasanna v. 9 i. 3 p. 333 - 353
Frequent value encoding for low power data buses
by: Jun Yang, Rajiv Gupta, Chuanjun Zhang v. 9 i. 3 p. 354 - 384
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
by: Ali Dasdan v. 9 i. 4 p. 385 - 418
Cache optimization for embedded processor cores: An analytical approach
by: Arijit Ghosh, Tony Givargis v. 9 i. 4 p. 419 - 440
Coordinated parallelizing compiler optimizations and high-level synthesis
by: Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau v. 9 i. 4 p. 441 - 470
Reusing an on-chip network for the test of core-based systems
by: Érika F. Cota, Luigi Carro, Marcelo Lubaszewski v. 9 i. 4 p. 471 - 499
Achieving high encoding efficiency with partial dynamic LFSR reseeding
by: C. V. Krishna, Abhijit Jas, Nur A. Touba v. 9 i. 4 p. 500 - 516
Segmented channel routability via satisfiability
by: William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Andrew A. Kennings, Alan J. Coppola v. 9 i. 4 p. 517 - 528

2003

Path delay fault testing using test points
by: Spyros Tragoudas, N. Denny v. 8 i. 1 p. 1 - 10
Analysis of FPGA/FPIC switch modules
by: Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong v. 8 i. 1 p. 11 - 37
Design theory and implementation for low-power segmented bus systems
by: Wen-Ben Jone, J. S. Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen v. 8 i. 1 p. 38 - 54
Floorplan representations: Complexity and connections
by: Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald Graham v. 8 i. 1 p. 55 - 80
Transistor placement for noncomplementary digital VLSI cell synthesis
by: Michael A. Riepe, Karem A. Sakallah v. 8 i. 1 p. 81 - 107
On the properties of the input pattern fault model
by: Ronald D. Blanton, John P. Hayes v. 8 i. 1 p. 108 - 124
Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications
by: Tanja Van Achteren, Francky Catthoor, Rudy Lauwereins, Geert Deconinck v. 8 i. 1 p. 125 - 139
Tutorial: Compiling concurrent languages for sequential processors
by: Stephen A. Edwards v. 8 i. 2 p. 141 - 187
Rectilinear block placement using B*-trees
by: Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang v. 8 i. 2 p. 188 - 202
Minimum delay optimization for domino circuits - a coupling-aware approach
by: Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang v. 8 i. 2 p. 202 - 213
Compacting sequences with invariant transition frequencies
by: Ali Pinar, C. L. Liu v. 8 i. 2 p. 214 - 221
Sequential optimization in the absence of global reset
by: Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton v. 8 i. 2 p. 222 - 251
Compiler optimization on VLIW instruction scheduling for low power
by: Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai v. 8 i. 2 p. 252 - 268
On the hardware-software partitioning problem: System modeling and partitioning techniques
by: Marisa Luisa López-Vallejo, Juan Carlos López v. 8 i. 3 p. 269 - 297
Gravity: Fast placement for 3-D VLSI
by: Stefan Thomas Obenaus, Ted H. Szymanski v. 8 i. 3 p. 298 - 315
Congestion reduction during placement with provably good approximation bound
by: Xiaojian Yang, Maogang Wang, Ryan Kastner, Soheil Ghiasi, Majid Sarrafzadeh v. 8 i. 3 p. 316 - 333
Synthesis of saturation arithmetic architectures
by: George A. Constantinides, Peter Y. K. Cheung, Wayne Luk v. 8 i. 3 p. 334 - 354
Constraints-driven scheduling and resource assignment
by: Krzysztof Kuchcinski v. 8 i. 3 p. 355 - 383
Address code generation for DSP instruction-set architectures
by: J.-Y. Lee, I.-C. Park v. 8 i. 3 p. 384 - 395
Introduction
by: Shishpal Rawat, Hans-Joachim Wunderlich v. 8 i. 4 p. 397 - 398
SOC test architecture design for efficient utilization of test bandwidth
by: Sandeep Kumar Goel, Erik Jan Marinissen v. 8 i. 4 p. 399 - 429
Test vector decomposition-based static compaction algorithms for combinational circuits
by: Aiman H. El-Maleh, Yahya E. Osais v. 8 i. 4 p. 430 - 459
On test data volume reduction for multiple scan chain designs
by: Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz v. 8 i. 4 p. 460 - 469
Test data compression using dictionaries with selective entries and fixed-length indices
by: Lei Li, Krishnendu Chakrabarty, Nur A. Touba v. 8 i. 4 p. 470 - 490
Multimode scan: Test per clock BIST for IP cores
by: Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan v. 8 i. 4 p. 491 - 505
Testing high-performance pipelined circuits with slow-speed testers
by: Muhammad Nummer, Manoj Sachdev v. 8 i. 4 p. 506 - 521
BIST and production testing of ADCs using imprecise stimulus
by: Kumar Parthasarathy, Turker Kuyel, Dana Price, Le Jin, Degang Chen, Randall L. Geiger v. 8 i. 4 p. 522 - 545
A circuit level fault model for resistive bridges
by: Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker v. 8 i. 4 p. 546 - 559
A data acquisition methodology for on-chip repair of embedded memories
by: Dirk Niggemeyer, Elizabeth M. Rudnick v. 8 i. 4 p. 560 - 576
A multiple bit upset tolerant SRAM memory
by: Gustavo Neuberger, Fernanda Gusmão de Lima, Luigi Carro, Ricardo Augusto da Luz Reis v. 8 i. 4 p. 577 - 590

2002

General technology mapping for field-programmable gate arrays based on lookup tables
by: Amit Chowdhary, John P. Hayes v. 7 i. 1 p. 1 - 32
ATPG tools for delay faults at the functional level
by: Maria Michael, Spyros Tragoudas v. 7 i. 1 p. 33 - 57
Prefetching for improved bus wrapper performance in cores
by: Roman L. Lysecky, Frank Vahid v. 7 i. 1 p. 58 - 90
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
by: Shantanu Dutt, Wenyong Deng v. 7 i. 1 p. 91 - 121
Microarchitectural synthesis of performance-constrained, low-power VLSI designs
by: Laurence Goodby, Alex Orailoglu, Paul M. Chau v. 7 i. 1 p. 122 - 136
Satisfiability models and algorithms for circuit delay computation
by: Luís Guerra e Silva, João P. Marques Silva, L. Miguel Silveira, Karem A. Sakallah v. 7 i. 1 p. 137 - 158
Constructing and exploiting linear schedules with prescribed parallelism
by: Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien v. 7 i. 1 p. 159 - 172
A fast algorithm for context-aware buffer insertion
by: Ashok Jagannathan, Sung-Woo Hur, John Lillis v. 7 i. 1 p. 173 - 188
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications
by: Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy v. 7 i. 1 p. 189 - 216
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs
by: Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai v. 7 i. 1 p. 217 - 230
Monotone bipartitioning problem in a planar point set with applications to VLSI
by: Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya v. 7 i. 2 p. 231 - 248
Initializability analysis of synchronous sequential circuits
by: Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero v. 7 i. 2 p. 249 - 264
Logic transformation for low-power synthesis
by: Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu v. 7 i. 2 p. 265 - 283
Fast placement approaches for FPGAs
by: Russell Tessier v. 7 i. 2 p. 284 - 305
Technology mapping algorithms for domino logic
by: Min Zhao, Sachin S. Sapatnekar v. 7 i. 2 p. 306 - 335
Global array reference allocation
by: Guido Araujo, Guilherme Ottoni, Marcelo H. Cintra v. 7 i. 2 p. 336 - 357
UST/DME: a clock tree router for general skew constraints
by: Chung-Wen Albert Tsao, Cheng-Kok Koh v. 7 i. 3 p. 359 - 379
Efficient scheduling of conditional behaviors for high-level synthesis
by: Apostolos A. Kountouris, Christophe Wolinski v. 7 i. 3 p. 380 - 412
Partitioning sequential programs for CAD using a three-step approach
by: Frank Vahid v. 7 i. 3 p. 413 - 429
Cluster assignment for high-performance embedded VLIW processors
by: Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana v. 7 i. 3 p. 430 - 454
Estimation of state line statistics in sequential circuits
by: Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj v. 7 i. 3 p. 455 - 473
False-noise analysis using logic implications
by: Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov v. 7 i. 3 p. 474 - 498
Guest editorial
by: Majid Sarrafzadeh, Rajeev Jayaraman v. 7 i. 4 p. 499 - 500
BDD-based logic synthesis for LUT-based FPGAs
by: Navin Vemuri, Priyank Kalla, Russell Tessier v. 7 i. 4 p. 501 - 525
Reduction design for generic universal switch blocks
by: Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong v. 7 i. 4 p. 526 - 546
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
by: Andreas Dandalis, Viktor K. Prasanna v. 7 i. 4 p. 547 - 562
Behavioral synthesis of field programmable analog array circuits
by: Haibo Wang, Sarma B. K. Vrudhula v. 7 i. 4 p. 563 - 604
Instruction generation for hybrid reconfigurable systems
by: Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh v. 7 i. 4 p. 605 - 627
Performance-driven placement for dynamically reconfigurable FPGAs
by: Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang v. 7 i. 4 p. 628 - 642
Efficient circuit clustering for area and power reduction in FPGAs
by: Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska v. 7 i. 4 p. 643 - 663
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
by: Shantanu Dutt, Vinay Verma, Hasan Arslan v. 7 i. 4 p. 664 - 693

2001

Performance-constrained hierarchical pipelining for behaviors, loops, and operations
by: Smita Bakshi, Daniel Gajski v. 6 i. 1 p. 1 - 25
Optimal test access architectures for system-on-a-chip
by: Krishnendu Chakrabarty v. 6 i. 1 p. 26 - 49
Architecture-level power estimation and design experiments
by: Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa v. 6 i. 1 p. 50 - 66
POSE: a parallel object-oriented synthesis environment
by: Pao-Ann Hsiung v. 6 i. 1 p. 67 - 92
Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors
by: Ing-Jer Huang v. 6 i. 1 p. 93 - 121
A mapping algorithm for computer-assisted exploration in the design of embedded systems
by: Evaggelinos P. Mariatos, Alexios N. Birbas, Michael K. Birbas v. 6 i. 1 p. 122 - 147
Data and memory optimization techniques for embedded systems
by: Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg v. 6 i. 2 p. 149 - 206
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
by: Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee v. 6 i. 2 p. 207 - 225
Intrinsic response for analog module testing using an analog testability bus
by: Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou v. 6 i. 2 p. 226 - 243
Verifying sequential equivalence using ATPG techniques
by: Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen v. 6 i. 2 p. 244 - 275
Processor modeling and code selection for retargetable compilation
by: Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens v. 6 i. 3 p. 277 - 307
Von Neumann hybrid cellular automata for generating deterministic test sequences
by: Dimitrios Kagaris, Spyros Tragoudas v. 6 i. 3 p. 308 - 321
Constrained polygon transformations for incremental floorplanning
by: Swanwa Liao, Mario A. Lopez, Dinesh P. Mehta v. 6 i. 3 p. 322 - 342
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
by: Chris Chu, D. F. Wong v. 6 i. 3 p. 343 - 371
Efficient list-approximation techniques for floorplan area minimization
by: Xiaobo Hu, Danny Z. Chen, Rajeshkumar S. Sambandam v. 6 i. 3 p. 372 - 400
Integrated test of interacting controllers and datapaths
by: Mehrdad Nourani, Joan Carletta, Christos A. Papachristou v. 6 i. 3 p. 401 - 422
Introducing redundant computations in RTL data paths for reducing BIST resources
by: Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer v. 6 i. 3 p. 423 - 445
Slicible rectangular graphs and their optimal floorplans
by: Parthasarathi Dasgupta, Susmita Sur-Kolay v. 6 i. 4 p. 447 - 470
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists
by: Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty v. 6 i. 4 p. 471 - 489
A fast approach to computing exact solutions to the resource-constrained scheduling problem
by: M. Narasimhan, J. Ramanujam v. 6 i. 4 p. 490 - 500
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs
by: Ramesh Karri, Balakrishnan Iyer v. 6 i. 4 p. 505 - 515
Optimal design of synchronous circuits using software pipelining techniques
by: François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer v. 6 i. 4 p. 516 - 532
On the fundamental limitations of transformational design
by: Jeroen Voeten v. 6 i. 4 p. 533 - 552
Data memory design and exploration for low-power embedded systems
by: Wen-Tsong Shiue, Sathishkumar Udayanarayanan, Chaitali Chakrabarti v. 6 i. 4 p. 553 - 568
Using complete-1-distinguishability for FSM equivalence checking
by: Pranav Ashar, Aarti Gupta, Sharad Malik v. 6 i. 4 p. 569 - 590
Optimizing designs containing black boxes
by: Tai-Hung Liu, Adnan Aziz, Vigyan Singhal v. 6 i. 4 p. 591 - 601
Forced simulation: A technique for automating component reuse in embedded systems
by: Partha S. Roop, Arcot Sowmya, S. Ramesh v. 6 i. 4 p. 602 - 628
An exact solution to the minimum size test pattern problem
by: Paulo F. Flores, Horácio C. Neto, João P. Marques Silva v. 6 i. 4 p. 629 - 644

2000

A code-motion pruning technique for global scheduling
by: Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess v. 5 i. 1 p. 1 - 38
Multiway FPGA partitioning by fully exploiting design hierarchy
by: Wen-Jong Fang, Allen C.-H. Wu v. 5 i. 1 p. 34 - 50
CMAPS: a cosynthesis methodology for application-oriented parallel systems
by: Pao-Ann Hsiung v. 5 i. 1 p. 51 - 81
On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs
by: Dinesh P. Mehta, Naveed A. Sherwani v. 5 i. 1 p. 82 - 97
Power-delay optimizations in gate sizing
by: Sachin S. Sapatnekar, Weitong Chuang v. 5 i. 1 p. 98 - 114
System-level power optimization: techniques and tools
by: Luca Benini, Giovanni De Micheli v. 5 i. 2 p. 115 - 192
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
by: Jason Cong, Yean-Yow Hwang v. 5 i. 2 p. 193 - 225
A predictive system shutdown method for energy saving of event-driven computation
by: Chi-Hong Hwang, Allen C.-H. Wu v. 5 i. 2 p. 226 - 241
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
by: Ashok Sudarsanam, Sharad Malik v. 5 i. 2 p. 242 - 264
Editorial
by: Mary Jane Irwin v. 5 i. 3 p. 265 - 266
Power optimization of technology-dependent circuits based on symbolic computation of logic implications
by: R. Iris Bahar, Ernest T. Lampe, Enrico Macii v. 5 i. 3 p. 267 - 293
Allocation of FIFO structures in RTL data paths
by: M. Balakrishnan, Heman Khanna v. 5 i. 3 p. 294 - 310
Synthesis of low-power selectively-clocked systems from high-level specification
by: Luca Benini, Giovanni De Micheli v. 5 i. 3 p. 311 - 321
Efficient optimal design space characterization methodologies
by: Stephen A. Blythe, Robert A. Walker v. 5 i. 3 p. 322 - 336
Regression-based RTL power modeling
by: Alessandro Bogliolo, Luca Benini, Giovanni De Micheli v. 5 i. 3 p. 337 - 372
Retiming-based factorization for sequential logic optimization
by: Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski v. 5 i. 3 p. 373 - 398
Hardware/software synthesis of formal specifications in codesign of embedded systems
by: Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni v. 5 i. 3 p. 399 - 432
Timing-driven routing for symmetrical array-based FPGAs
by: Yao-Wen Chang, Kai Zhu, D. F. Wong v. 5 i. 3 p. 433 - 450
Modeling layout tools to derive forward estimates of area and delay at the RTL level
by: Donald S. Gelosh, Dorothy E. Setliff v. 5 i. 3 p. 451 - 491
A codesign back-end approach for embedded system design
by: Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet v. 5 i. 3 p. 492 - 509
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
by: Avaneendra Gupta, John P. Hayes v. 5 i. 3 p. 510 - 547
Dynamic state traversal for sequential circuit test generation
by: Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel v. 5 i. 3 p. 548 - 565
High-level library mapping for memories
by: Pradip K. Jha, Nikil D. Dutt v. 5 i. 3 p. 566 - 603
Optimizing computations for effective block-processing
by: Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak v. 5 i. 3 p. 604 - 630
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
by: David E. Long, Mahesh A. Iyer, Miron Abramovici v. 5 i. 3 p. 631 - 657
Stochastic sequential machine synthesis with application to constrained sequence generation
by: Diana Marculescu, Radu Marculescu, Massoud Pedram v. 5 i. 3 p. 658 - 681
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
by: Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau v. 5 i. 3 p. 682 - 704
Environment modeling and language universality
by: Richard Raimi, Ramin Hojati, Kedar S. Namjoshi v. 5 i. 3 p. 705 - 725
Three-layer bubble-sorting-based nonManhattan channel routing
by: Jin-Tai Yan v. 5 i. 3 p. 726 - 734
Efficient routability check algorithms for segmented channel routing
by: Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai v. 5 i. 3 p. 735 - 747
Guest Editorial
by: Peter Marwedel v. 5 i. 4 p. 749 - 751
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats
by: Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau v. 5 i. 4 p. 752 - 773
Constraint analysis for code generation: basic techniques and applications in FACTS
by: Koen Van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess v. 5 i. 4 p. 774 - 793
Graph-based code selection techniques for embedded processors
by: Rainer Leupers, Steven Bashford v. 5 i. 4 p. 794 - 814
Retargetable compiled simulation of embedded processors using a machine description language
by: Stefan Pees, Andreas Hoffmann, Heinrich Meyr v. 5 i. 4 p. 815 - 834

1999

Bus-based communication synthesis on system level
by: Michael Gasteier, Manfred Glesner v. 4 i. 1 p. 1 - 11
A text-compression-based method for code size minimization in embedded systems
by: Stan Liao, Srinivas Devadas, Kurt Keutzer v. 4 i. 1 p. 12 - 38
On the crossing distribution problem
by: Xiaoyu Song, Yuke Wang v. 4 i. 1 p. 39 - 51
Two-level logic minimization for low power
by: Jyh-Mou Tseng, Jing-Yang Jou v. 4 i. 1 p. 52 - 69
Procedure cloning: a transformation for improved system-level functional partitioning
by: Frank Vahid v. 4 i. 1 p. 70 - 96
Power reduction and power-delay trade-offs using logic transformations
by: Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly v. 4 i. 1 p. 97 - 121
Formal verification in hardware design: a survey
by: Christoph Kern, Mark R. Greenstreet v. 4 i. 2 p. 123 - 193
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults
by: Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang v. 4 i. 2 p. 194 - 218
Behavioral synthesis of combinational logic using spectral-based heuristics
by: Mitchell A. Thornton, V. S. S. Nair v. 4 i. 2 p. 219 - 230
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining
by: Wei-Kai Cheng, Youn-Long Lin v. 4 i. 3 p. 231 - 256
Performance estimation of embedded software with instruction cache modeling
by: Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe v. 4 i. 3 p. 257 - 279
Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis
by: C.-J. Richard Shi, Michael W. Tian v. 4 i. 3 p. 280 - 312
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs
by: Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich v. 4 i. 3 p. 313 - 350
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
by: Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi v. 4 i. 4 p. 351 - 375
A flexible datapath allocation method for architectural synthesis
by: Kyumyung Choi, Steven P. Levitan v. 4 i. 4 p. 376 - 404
Power optimization using divide-and-conquer techniques for minimization of the number of operations
by: Inki Hong, Miodrag Potkonjak, Ramesh Karri v. 4 i. 4 p. 405 - 429
A methodology and algorithms for the design of hard real-time multitasking ASICs
by: Miodrag Potkonjak, Wayne Wolf v. 4 i. 4 p. 430 - 459

1998

Measurement and analysis of sequential design processes
by: Eric W. Johnson, Jay B. Brockman v. 3 i. 1 p. 1 - 20
Semantics and verification of action diagrams with linear timing
by: Karim Khordoc, Eduard Cerny v. 3 i. 1 p. 21 - 50
A new viewpoint on code generation for directed acyclic graphs
by: Stan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, Srinivas Devadas v. 3 i. 1 p. 51 - 75
Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems
by: C.-J. Richard Shi, Janusz A. Brzozowski v. 3 i. 1 p. 76 - 107
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems
by: Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen v. 3 i. 2 p. 109 - 135
Code generation for fixed-point DSPs
by: Guido Araujo, Sharad Malik v. 3 i. 2 p. 136 - 161
Estimation of lower bounds in scheduling algorithms for high-level synthesis
by: Giri Tiruvuri, Moon Chung v. 3 i. 2 p. 162 - 180
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance
by: Frank Vahid, Thuy Dm Le, Yu-Chin Hsu v. 3 i. 2 p. 181 - 208
Breakpoints and breakpoint detection in source-level emulation
by: Gernot Koch, Wolfgang Rosenstiel, Udo Kebschull v. 3 i. 2 p. 209 - 230
Functional test generation for delay faults in combinational circuits
by: Irith Pomeranz, Sudhakar M. Reddy v. 3 i. 2 p. 231 - 248
Structural diagnosis of interconnects by coloring
by: Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi v. 3 i. 2 p. 249 - 271
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures
by: Dinesh P. Mehta v. 3 i. 2 p. 272 - 284
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
by: Subhrajit Bhattacharya, Sujit Dey, Franc Brglez v. 3 i. 2 p. 285 - 307
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
by: Gianpiero Cabodi, Paolo Camurati, Stefano Quer v. 3 i. 3 p. 309 - 340
Bounded-skew clock and Steiner routing
by: Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao v. 3 i. 3 p. 341 - 388
Confidence analysis for defect-level estimation of VLSI random testing
by: Wen-Ben Jone, K. S. Tsai v. 3 i. 3 p. 389 - 407
Rate analysis for embedded systems
by: Anmol Mathur, Ali Dasdan, Rajesh K. Gupta v. 3 i. 3 p. 408 - 436
Optimal clock period FPGA technology mapping for sequential circuits
by: Peichen Pan, C. L. Liu v. 3 i. 3 p. 437 - 462
The edge-based design rule model revisited
by: Michael A. Riepe, Karem A. Sakallah v. 3 i. 3 p. 463 - 486
Eliminating false loops caused by sharing in control path
by: Alan Su 0002, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee v. 3 i. 3 p. 487 - 495
Optimal river routing with crosstalk constraints
by: Hai Zhou, D. F. Wong v. 3 i. 3 p. 496 - 514
Modeling reactive systems in Java
by: Claudio Passerone, Claudio Sansoè, Luciano Lavagno, Patrick C. McGeer, Jonathan Martin, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli v. 3 i. 4 p. 515 - 523
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays
by: Li-C. Wang, Magdy S. Abadir, Jing Zeng v. 3 i. 4 p. 524 - 532
A timing-driven design and validation methodology for embedded real-time systems
by: Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta v. 3 i. 4 p. 533 - 553
ATM switch design by high-level modeling, formal verification and high-level synthesi
by: Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee v. 3 i. 4 p. 554 - 562
Specification and verification of pipelining in the ARM2 RISC microprocessor
by: James K. Huggins, David Van Campenhout v. 3 i. 4 p. 563 - 580
High-level design verification of microprocessors via error modeling
by: David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown v. 3 i. 4 p. 581 - 599
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming
by: Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee v. 3 i. 4 p. 600 - 625
EXFI: a low-cost fault injection system for embedded microprocessor-based boards
by: Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda v. 3 i. 4 p. 626 - 634

1997

Recent developments in high-level synthesis
by: Youn-Long Lin v. 2 i. 1 p. 2 - 21
Model refinement for hardware-software codesign
by: Jie Gong, Daniel Gajski, Smita Bakshi v. 2 i. 1 p. 22 - 41
AGENTS a distributed client-server system for leaf cell generation
by: Dilvan de Abreu Moreira, Les T. Walczowski v. 2 i. 1 p. 42 - 61
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration
by: Henrik Esbensen, Ernest S. Kuh v. 2 i. 1 p. 62 - 80
Scheduling techniques for variable voltage low power designs
by: Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu v. 2 i. 2 p. 81 - 97
Functional design for testability of control-dominated architectures
by: Franco Fummi, U. Rovati, Donatella Sciuto v. 2 i. 2 p. 98 - 122
Parallel logic simulation on a network of workstations using parallel virtual machine
by: Maciek Kormicki, Ausif Mahmood, Bradley S. Carlson v. 2 i. 2 p. 123 - 134
Hmap: a fast mapper for EPGAs using extended GBDD hash tables
by: Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen v. 2 i. 2 p. 135 - 150
Board-level multiterminal net routing for FPGA-based logic emulation
by: Wai-Kei Mak, D. F. Wong v. 2 i. 2 p. 151 - 167
Analysis of RC interconnections under ramp input
by: Andrew B. Kahng, Sudhakar Muddu v. 2 i. 2 p. 168 - 192
A survey of Boolean matching techniques for library binding
by: Luca Benini, Giovanni De Micheli v. 2 i. 3 p. 193 - 226
Datapath scheduling with multiple supply voltages and level converters
by: Mark C. Johnson, Kaushik Roy v. 2 i. 3 p. 227 - 248
Event propagation conditions in circuit delay computation
by: Hakan Yalcin, John P. Hayes v. 2 i. 3 p. 249 - 280
Algorithms to compute bridging fault coverage of IDDQ test sets
by: Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel v. 2 i. 3 p. 281 - 305
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
by: Min Xu, Fadi J. Kurdahi v. 2 i. 4 p. 312 - 343
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions
by: Michael Münch, Norbert Wehn, Manfred Glesner v. 2 i. 4 p. 344 - 364
A codesign experiment in acoustic echo cancellation GMDF
by: L. Freund, M. Israel, Frédéric Rousseau, J. M. Bergé, Michel Auguin, Cécile Belleudy, Guy Gogniat v. 2 i. 4 p. 365 - 383
Memory data organization for improved cache performance in embedded processor applications
by: Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau v. 2 i. 4 p. 384 - 409
Code placement techniques for cache miss rate reduction
by: Hiroyuki Tomiyama, Hiroto Yasuura v. 2 i. 4 p. 410 - 429

1996

Power minimization in IC design: principles and applications
by: Massoud Pedram v. 1 i. 1 p. 3 - 56
Automatic generation of functional vectors using the extended finite state machine model
by: Kwang-Ting Cheng, A. S. Krishnakumar v. 1 i. 1 p. 57 - 79
Universal switch modules for FPGA design
by: Yao-Wen Chang, D. F. Wong, C. K. Wong v. 1 i. 1 p. 80 - 101
Series-parallel functions and FPGA logic module design
by: Shashidhar Thakur, D. F. Wong v. 1 i. 1 p. 102 - 122
Optimal folding of standard and custom cells
by: Venkat Thanvantri, Sartaj Sahni v. 1 i. 1 p. 123 - 143
Combinational logic synthesis for LUT based field programmable gate arrays
by: Jason Cong, Yuzheng Ding v. 1 i. 2 p. 145 - 204
From VHDL to efficient and first-time-right designs: a formal approach
by: Peter F. A. Middelhoek, Sreeranga P. Rajan v. 1 i. 2 p. 205 - 250
Optimal register assignment to loops for embedded code generation
by: David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy v. 1 i. 2 p. 251 - 279
Transistor reordering for power minimization under delay constraint
by: S. C. Prasad, Kaushik Roy v. 1 i. 2 p. 280 - 300
Object-oriented cosynthesis of distributed embedded systems
by: Wayne Wolf v. 1 i. 3 p. 301 - 314
Low power realization of finite state machines - a decomposition approach
by: Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu v. 1 i. 3 p. 315 - 340
A fast algorithm for minimizing FPGA combinational and sequential modules
by: Dimitrios Kagaris, Spyros Tragoudas v. 1 i. 3 p. 341 - 351
An optimal clock period selection method based on slack minimization criteria
by: En-Shou Chang, Daniel Gajski, Sanjiv Narayan v. 1 i. 3 p. 352 - 370
Efficient decomposition of polygons into L-shapes with application to VLSI layouts
by: Mario A. Lopez, Dinesh P. Mehta v. 1 i. 3 p. 371 - 395
Register estimation in unscheduled dataflow graphs
by: R. Moreno, Román Hermida, Milagros Fernández v. 1 i. 3 p. 396 - 403
Gate-level test generation for sequential circuits
by: Kwang-Ting Cheng v. 1 i. 4 p. 405 - 442
A recursive technique for computing lower-bound performance of schedules
by: Michel Langevin, Eduard Cerny v. 1 i. 4 p. 443 - 455
The Unison algorithm: fast evaluation of Boolean expressions
by: Rok Sosic, Jun Gu, Robert R. Johnson v. 1 i. 4 p. 456 - 477
Optimal wiresizing for interconnects with multiple sources
by: Jason Cong, Lei He v. 1 i. 4 p. 478 - 511
Rectilinear Steiner trees on a checkerboard
by: Joseph L. Ganley, James P. Cohoon v. 1 i. 4 p. 512 - 522