Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

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Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

Randal E. Bryant, Steven M. German, Miroslav N. Velev

Journal Title: ACM Transactions on Computer Logic

Date: 2001

Volume: 2

Issue: 1

p. 93 - 134

We have been looking for this document on the Web. We think we have found the following, freely available version(s) of it:

http://arxiv.org/pdf/cs.LO/9910014

http://reports-archive.adm.cs.cmu.edu/anon/1999/CMU-CS-99-115.pdf

http://reports-archive.adm.cs.cmu.edu/anon/1999/CMU-CS-99-115.ps

For further information about this item go to:

http://doi.acm.org/10.1145/371282.371364

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