International Symposium on Low Power Electronics and Design
2004
- Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOSby: Hari Ananthan, Chris H. Kim, Kaushik Roy
- Application adaptive energy efficient clustered architecturesby: Diana Marculescu
- Approaches to run-time and standby mode leakage reduction in global busesby: Rahul Rao, Kanak Agarwal, Dennis Sylvester, Richard Brown, Kevin J. Nowka, Sani R. Nassif
- Preemption-aware dynamic voltage scaling in hard real-time systemsby: Woonseok Kim, Jihong Kim, Sang Lyul Min
- Leakage power reduction by dual-vth designs under probabilistic analysis of vth variationby: Michael Liu, Wei-Shen Wang, Michael Orshansky
- Managing standby and active mode leakage power in deep sub-micron designby: Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty
- A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approachby: Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu
- Battery life challenges on future mobile notebook platformsby: Shreekant (Ticky) Thakkar
- Efficient adaptive voltage scaling system through on-chip critical path emulationby: Mohamed Elgebaly, Manoj Sachdev
- Soft error and energy consumption interactions: a data cache perspectiveby: Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
- A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variationsby: Songqing Zhang, Vineet Wason, Kaustav Banerjee
- Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generationby: Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald Gardner, Siva Narendra, Tanay Karnik, Vivek De
- Post-layout leakage power minimization based on distributed sleep transistor insertionby: Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
- Characterizing and modeling minimum energy operation for subthreshold circuitsby: Benton H. Calhoun, Anantha Chandrakasan
- Why hot chips are no longer "cool"by: Ray Bryant
- Memory-aware energy-optimal frequency assignment for dynamic supply voltage scalingby: Youngjin Cho, Naehyuck Chang
- Improved clock-gating through transparent pipeliningby: Hans M. Jacobson
- Nanoscale CMOS circuit leakage power reduction by double-gate deviceby: Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
- SEPAS: a highly accurate energy-efficient branch predictorby: Amirali Baniasadi, Andreas Moshovos
- Minimizing power consumption and complexity in a programmable transmit filter bank for OFDMby: Alireza Mehrnia, Babak Daneshrad
- HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reductionby: Chia-Lin Yang, Chien-Hao Lee
- Reducing pipeline energy demands with local DVS and dynamic retimingby: Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge
- Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbpsby: Marian Verhelst, Wim Vereecken, Michiel Steyaert, Wim Dehaene
- Constant-load energy recovery memory for efficient high-speed operationby: Joohee Kim, Marios C. Papaefthymiou
- Energy-aware demand paging on NAND flash-based embedded storagesby: Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jin-Soo Kim
- Understanding nanoscale conductorsby: Supriyo Datta
- FSM--based power modeling of wireless protocols: the case of bluetoothby: Luca Negri, Mariagiovanna Sami, David Macii, Alessandra Terranegra
- 4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensorsby: Stefanos Kaxiras, Polychronis Xekalakis
- Experimental measurement of a novel power gating structure with intermediate power saving modeby: Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz
- A way-halting cache for low-energy high-performance systemsby: Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
- Microarchitectural techniques for power gating of execution unitsby: Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
- Creating a power-aware structured ASICby: R. Reed Taylor, Herman Schmit
- Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulationby: Chuang Zhang, Dongsheng Ma, Ashok Srivastava
- The design of a low power asynchronous multiplierby: Yijun Liu, Stephen B. Furber
- Power-optimal pipelining in deep submicron technologyby: Seongmoo Heo, Krste Asanovic
- Understanding the energy efficiency of simultaneous multithreadingby: Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
- Maximizing efficiency of solar-powered systems by load matchingby: Dexin Li, Pai H. Chou
- Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimizationby: Kim M. Hazelwood, David Brooks
- Low-power fixed-width array multipliersby: Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang
- Experience with a low power wireless mobile computing platformby: Vijay Raghunathan, Trevor Pering, Roy Want, Alex Nguyen, Peter Jensen
- On optimality of adiabatic switching in MOS energy-recovery circuitby: Baohua Wang, Pinaki Mazumder
- A novel continuous-time common-mode feedback for low-voltage switched-OPAMPby: M. Ali-Bakhshian, K. Sadeghi
- Dynamic voltage and frequency scaling based on workload decompositionby: Kihwan Choi, Ramakrishna Soma, Massoud Pedram
- Any-time probabilistic switching model using bayesian networksby: Shiva Shankar Ramani, Sanjukta Bhanja
- The impact of variability on powerby: Sani R. Nassif
- 2.45 GHz power and data transmission for a low-power autonomous sensors platformby: Stefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti
- Application-level prediction of battery dissipationby: Chandra Krintz, Ye Wen, Richard Wolski
- Impact of technology scaling on energy aware execution cache-based microarchitecturesby: Emil Talpes, Diana Marculescu
- Delayed line bus scheme: a low-power bus scheme for coupled on-chip busesby: Maged Ghoneima, Yehea I. Ismail
- Active mode leakage reduction using fine-grained forward body biasing strategyby: Vishal Khandelwal, Ankur Srivastava
- ESACW: an adaptive algorithm for transmission power reduction in wireless networksby: Hang Su, Peiliang Qiu, Qinru Qiu
- Delay optimal low-power circuit clustering for FPGAs with dual supply voltagesby: Deming Chen, Jason Cong
- An efficient voltage scaling algorithm for complex SoCs with few number of voltage modesby: Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
- Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfacesby: Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino
- Dynamic voltage scaling for systemwide energy minimization in real-time embedded systemsby: Ravindra Jejurikar, Rajesh K. Gupta
- Architecting voltage islands in core-based system-on-a-chip designsby: Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu
- Device optimization for ultra-low power digital sub-threshold operationby: Bipul C. Paul, Arijit Raychowdhury, Kaushik Roy
- A new algorithm for improved VDD assignment in low power dual VDD systemsby: Sarvesh Kulkarni, Ashish Srivastava, Dennis Sylvester
- Design and implementation of correlating cachesby: Arindam Mallik, Matthew C. Wildrick, Gokhan Memik
- Location cache: a low-power L2 cache systemby: Rui Min, Wen-Ben Jone, Yiming Hu
- Balanced energy optimizationby: John Cornish
- Microarchitectural power modeling techniques for deep sub-micron microprocessorsby: Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
- Reducing radio energy consumption of key management protocols for wireless sensor networksby: Bo-Cheng Lai, David Hwang, Sungha Pete Kim, Ingrid Verbauwhede
- A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologiesby: Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
- On optimality of adiabatic switching in MOS energy-recovery circuitby: Baohua Wang, Pinaki Mazumder
- Power utility maximization for multiple-supply systems by a load-matching switchby: Chulsung Park, Pai H. Chou
- Dynamic power management for streaming databy: Nathaniel Pettis, Le Cai, Yung-Hsiang Lu
- Low-power carry-select adder using adaptive supply voltage based on input vector patternsby: Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
- A CMOS even harmonic mixer with current reuse for low power applicationsby: Ming-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo
- Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systemsby: Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min
- Low-power asynchronous viterbi decoder for wireless applicationsby: Mohamed Kawokgy, C. Andre T. Salama
- A comparative study of MOS VCOs for low voltage high performance operationby: J. H. C. Zhan, J. S. Duster, Kevin T. Kornegay
- Spatial encoding circuit techniques for peak power reduction of on-chip high-performance busesby: Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
- Technology exploration for adaptive power and frequency scaling in 90nm CMOSby: Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
- Leakage and leakage sensitivity computation for combinational circuitsby: Emrah Acar, Anirudh Devgan, Rahul Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
- Estimating influence of data layout optimizations on SDRAM energy consumptionby: Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin
- Energy-efficient data scrambling on memory-processor interfacesby: Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino
- Understanding and minimizing ground bounce during mode transition of power gating structuresby: Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
- Simultaneous Vt selection and assignment for leakage optimizationby: Ankur Srivastava
- Power-aware scheduling of conditional task graphs in real-time multiprocessor systemsby: Dongkun Shin, Jihong Kim
- An ASIC design methodology with predictably low leakage, using leakage-immune standard cellsby: Nikhil Jayakumar, Sunil P. Khatri
- An MTCMOS design methodology and its application to mobile computingby: Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong
- UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSIby: Kyu-won Choi, Abhijit Chatterjee
- Analyzing the energy consumption of security protocolsby: Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
- Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experimentby: Masayuki Miyazaki, Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo, Takayuki Kawahara, Kazuo Yano
- Ambient intelligence: industrial research on a visionary conceptby: Werner Weber
- A semi-custom voltage-island technique and its application to high-speed serial linksby: Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman
- Reducing reorder buffer complexity through selective operand cachingby: Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
- Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiersby: Woo Young Choi, Jong Duk Lee, Byung-Gook Park
- Analysis of discharge techniques for multiple battery systemsby: Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov
- Strained-si devices and circuits for low-power applicationsby: Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
- A low-power design methodology for high-resolution pipelined analog-to-digital convertersby: Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei
- Low power coordination in wireless ad-hoc networksby: Farinaz Koushanfar, Abhijit Davare, Dai Tho Nguyen, Miodrag Potkonjak, Alberto L. Sangiovanni-Vincentelli
- Energy optimization techniques in cluster interconnectsby: Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das
- Energy characterization of a tiled architecture processor with on-chip networksby: Jason Sungtae Kim, Michael Bedford Taylor, Jason Miller, David Wentzlaff
- Exploiting compiler-generated schedules for energy savings in high-performance processorsby: Madhavi Valluri, Lizy Kurian John, Heather Hanson
- A low-power VLSI architecture for turbo decodingby: Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
- A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiersby: Mohammad M. Ahmadi, Reza Lotfi
- Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technologyby: Drew Guckenberger, Kevin T. Kornegay
- A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regimeby: Amit Agarwal, Kaushik Roy
- Low-power high-level synthesis for FPGA architecturesby: Deming Chen, Jason Cong, Yiping Fan
- Multivoltage scheduling with voltage-partitioned variable storageby: Amitabh Menon, S. K. Nandy, Mahesh Mehendale
- Elements of low power design for integrated systemsby: Sung-Mo Kang
- Microarchitecture level power and thermal simulation considering temperature dependent leakage modelby: Weiping Liao, Fei Li, Lei He
- Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimizationby: David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer
- Low power requirements for future digital life styleby: Ki Won Lee
- Reducing power density through activity migrationby: Seongmoo Heo, Kenneth Barr, Krste Asanovic
- Energy efficient D-TLB and data cache using semantic-aware multilateral partitioningby: Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram
- Exploiting program hotspots and code sequentiality for instruction cache leakage managementby: Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
- Design methodology for fine-grained leakage control in MTCMOSby: Ben Calhoun, Frank Honoré, Anantha Chandrakasan
- Energy-aware architectures for a real-valued FFT implementationby: Alice Wang, Anantha Chandrakasan
- Reducing translation lookaside buffer active powerby: Lawrence T. Clark, Byungwoo Choi, Michael Wilkerson
- A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technologyby: Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence Wagner
- Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessorsby: Yiran Chen, Kaushik Roy, Cheng-Kok Koh
- Full chip leakage estimation considering power supply and temperature variationsby: Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
- Low cost instruction cache designs for tag comparison eliminationby: Youtao Zhang, Jun Yang
- Temperature and process invariant MOS-based reference current generation circuits for sub-1V operationby: Stephen Tang, Siva Narendra, Vivek De
- Power efficient comparators for long arguments in superscalar processorsby: Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
- A systems approach to molecular electronicsby: James R. Heath
- Optimal body bias selection for leakage improvement and process compensation over different technology generationsby: Cassondra Neau, Kaushik Roy
- Routine based OS-aware microprocessor resource adaptation for run-time operating system power savingby: Tao Li, Lizy Kurian John
- Non redundant data cacheby: Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella
- Reducing instruction fetch energy with backwards branch control information and bufferingby: Jude A. Rivers, Sameh Asaad, John-David Wellman, Jaime H. Moreno
- Voltage scheduling under unpredictabilities: a risk management paradigmby: Azadeh Davoodi, Ankur Srivastava
- A clock delayed sleep mode domino logic for wide dynamic OR gateby: Kwang-Il Oh, Lee-Sup Kim
- Energy-aware memory allocation in heterogeneous non-volatile memory systemsby: Hyung Gyu Lee, Naehyuck Chang
- Lightweight set buffer: low power data cache for multimedia applicationby: Jun Yang, Youtao Zhang
- New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technologyby: Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
- Low power RF IC design for wireless communicationby: Domine Leenaerts
- Energy recovery clocking scheme and flip-flops for ultra low-energy applicationsby: Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
- Effective graph theoretic techniques for the generalized low power binding problemby: Azadeh Davoodi, Ankur Srivastava
- A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" techniqueby: H. A. Aslanzadeh, S. Mehrmanesh, M. B. Vahidfar, A. Q. Safarian, Reza Lotfi
- A power-aware SWDR cell for reducing cache write powerby: Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
- B#: a battery emulator and power profiling instrumentby: Pai H. Chou, Chulsung Park, Jae Park, Kien Pham, Jinfeng Liu
- Evolution of low power electronics and its future applicationsby: Tsugio Makimoto, Yoshio Sakai
- Branch prediction on demand: an energy-efficient solutionby: Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
- Checkpointing alternatives for high performance, power-aware processorsby: Andreas Moshovos
- Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noiseby: Michael D. Powell, T. N. Vijaykumar
- LPBP: low-power basis profile of the Java 2 Micro Editionby: Inseok Choi, Hyung Soo Kim, Heonshik Shin, Naehyuck Chang
- Pipeline stage unification: a low-energy consumption technique for future mobile processorsby: Hajime Shimada, Hideki Ando, Toshio Shimada
- Reducing energy and delay using efficient victim cachesby: Gokhan Memik, Glenn Reinman, William H. Mangione-Smith
- Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution timeby: Flavius Gruian, Krzysztof Kuchcinski
- Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologiesby: Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
- A forward body-biased low-leakage SRAM cache: device and architecture considerationsby: Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
- Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applicationsby: Mohammad Yavari, Omid Shoaei
- Level conversion for dual-supply systemsby: Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic
- Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysisby: Woonseok Kim, Jihong Kim, Sang Lyul Min
- A 225 MHz resonant clocked ASIC chipby: Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou
- An environmental energy harvesting framework for sensor networksby: Aman Kansal, Mani B. Srivastava
- On load latency in low-power cachesby: Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John
- A critical analysis of application-adaptive multiple clock processorsby: Emil Talpes, Diana Marculescu
- Microprocessor pipeline energy analysisby: Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger
- Low power startup circuits for voltage and current reference with zero steady state currentby: Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri
- Reducing data cache energy consumption via cached load/store queueby: Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau
- Leakage power modeling and optimization in interconnection networksby: Xuning Chen, Li-Shiuan Peh
- Statistical estimation of leakage current considering inter- and intra-die process variationby: Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester
- A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrateby: Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence Wagner
- A selective filter-bank TLB systemby: Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
- Efficient techniques for gate leakage estimationby: Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
- ILP-based optimization of sequential circuits for low powerby: Feng Gao, John P. Hayes
- A 0.75-mW analog processor IC for wireless biosignal monitorby: Chih-Jen Yen, Mely Chen Chi, Wen-Yaw Chung, Shing-Hao Lee
- A mixed-clock issue queue design for globally asynchronous, locally synchronous processor coresby: Venkata Syam P. Rapaka, Diana Marculescu
- The microarchitecture of a low power register fileby: Nam Sung Kim, Trevor N. Mudge
- ESTIMA: an architectural-level power estimator for multi-ported pipelined register filesby: Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm
- Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systemsby: Sung I. Park, Vijay Raghunathan, Mani B. Srivastava
- Low-voltage low-power high dB-linear CMOS exponential function generator using highly-linear V-I converterby: Quoc-Hoang Duong, Trung-Kien Nguyen, Sang-Gug Lee
- Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variationby: Saibal Mukhopadhyay, Kaushik Roy
- Energy-efficient instruction set synthesis for application-specific processorsby: Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
- A novel high frequency, high-efficiency, differential class-E power amplifier in 0.18mum CMOSby: Payam Heydari, Ying Zhang
- Oversampled gain-boostingby: Omid Oliaei
- Low-power color TFT LCD display for hand-held embedded systemsby: Inseok Choi, Hojun Shim, Naehyuck Chang
- Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model)by: Hyunsik Im
- Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximationsby: Rusell E. Henning, Chaitali Chakrabarti
- Modeling and analysis of leakage power considering within-die process variationsby: Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester
- Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2by: Afshin Abdollahi, Massoud Pedram, Farzan Fallah
- Conditional pre-charge techniques for power-efficient dual-edge clockingby: Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
- Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOSby: Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner
- Power-aware source routing protocol for mobile ad hoc networksby: Morteza Maleki, Karthik Dantu, Massoud Pedram
- Low-voltage memories for power-aware systemsby: Kiyoo Itoh
- Circuit-level techniques to control gate leakage for sub-100nm CMOSby: Fatih Hamzaoglu, Mircea R. Stan
- Power analysis techniques for SoC with improved wiring modelsby: Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
- Automated selective multi-threshold design for ultra-low standby applicationsby: Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
- Early evaluation techniques for low power bindingby: Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh
- Energy-efficient hybrid wakeup logicby: Michael C. Huang, Jose Renau, Josep Torrellas
- A power and resolution adaptive flash analog-to-digital converterby: Jincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim
- Tradeoffs in power-efficient issue queue designby: Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster
- Compact models for estimating microprocessor frequency and powerby: William C. Athas, Lynn Youngs, Andrew Reinhart
- Low-leakage asymmetric-cell SRAMby: Navid Azizi, Andreas Moshovos, Farid N. Najm
- An adaptive serial-parallel CAM architecture for low-power cache blocksby: Aristides Efthymiou, Jim D. Garside
- Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structuresby: Edgar G. Daylight, Sven Wuytack, Chantal Ykman-Couvreur, Francky Catthoor
- Contents provider-assisted dynamic voltage scaling for low energy multimedia applicationsby: Eui-Young Chung, Giovanni De Micheli, Luca Benini
- Battery lifetime prediction for energy-aware computingby: Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach
- Is nanoelectronics the future of microelectronics?by: Mark S. Lundstrom
- Reducing access energy of on-chip data memory considering active data bitwidthby: Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura
- Power estimation of sequential circuits using hierarchical colored hardware petri net modelingby: Ashok K. Murugavel, N. Ranganathan
- Towards energy-aware software-based fault tolerance in real-time systemsby: Osman S. Unsal, Israel Koren, C. Mani Krishna
- Activity-sensitive clock tree construction for low powerby: Chunhong Chen, Changjun Kang, Majid Sarrafzadeh
- Odd/even bus invert with two-phase transfer for buses with couplingby: Yan Zhang, John Lach, Kevin Skadron, Mircea R. Stan
- Low-power VLSI decoder architectures for LDPC codesby: Mohammad M. Mansour, Naresh R. Shanbhag
- Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levelsby: Victor V. Zyuban, Philip N. Strenski
- Energy recovering static memoryby: Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
- HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSIby: Kyu-won Choi, Abhijit Chatterjee
- Designing SoC'sby: Tobias Noll, Heinrich Meyr
- Saving energy with just in time instruction deliveryby: Tejas Karkhanis, James E. Smith, Pradip Bose
- TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessorsby: Magnus Ekman, Per Stenström, Fredrik Dahlgren
- High performance and low power FIR filter design based on sharing multiplicationby: Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
- Efficient estimation of signal transition activity in MAC architecturesby: Alberto García, Lukusa D. Kabulepa, Manfred Glesner
- Closed-loop adaptive voltage scaling controller for standard-cell ASICsby: Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen
- Discharge current steering for battery lifetime optimizationby: Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
- ±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode schemeby: Simon C. Li, Jimmy C. Cha
- Reducing energy consumption of video memory by bit-width compressionby: Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa
- A framework for energy-scalable communication in high-density wireless networksby: Rex Min, Anantha Chandrakasan
- Fine-grain CAM-tag cache resizing using miss tagsby: Michael Zhang, Krste Asanovic
- A history-based I-cache for low-energy multimedia applicationsby: Koji Inoue, Vasily G. Moshnyaga, Keikichi Murakami
- Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOSby: Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan
- Standby power management for a 0.18µm microprocessorby: Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci
- A low power normalized-LMS decision feedback equalizer for a wireless packet modemby: David Garrett, Chris Nicol, Andrew J. Blanksby, Chris Howland
- A preactivating mechanism for a VT-CMOS cache using address predictionby: Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
- Parametric timing and power macromodels for high level simulation of low-swing interconnectsby: Davide Bertozzi, Luca Benini, Bruno Riccò
- An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow modelby: Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo
- Novel modeling techniques for RTL power estimationby: Michael Eiermann, Walter Stechele
- Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessorsby: Chris H. Kim, Kaushik Roy
- Future directions in clocking multi-ghz systemsby: Vojin G. Oklobdzija, Jens Sparsø
- Design techniques for low power high bandwidth upconversion in CMOSby: Carl De Ranter, Michiel Steyaert
- A microarchitectural-level step-power analysis toolby: Wael El-Essawy, David H. Albonesi, Balaram Sinharoy
- High-level area estimationby: Kavel M. Büyüksahin, Farid N. Najm
- E2WFQ: an energy efficient fair scheduling policy for wireless systemsby: Vijay Raghunathan, Saurabh Ganeriwal, Curt Schurgers, Mani B. Srivastava
- Managing leakage for transient data: decay and quasi-static 4T memory cellsby: Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark
- Retiming-based logic synthesis for low-powerby: Yu-Lung Hsu, Sying-Jyan Wang
- Asymmetric-frequency clustering: a power-aware back-end for high-performance processorsby: Amirali Baniasadi, Andreas Moshovos
- A low-power digital matched filter for spread-spectrum systemsby: Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
- Low power integrated scan-retention mechanismby: Victor V. Zyuban, Stephen V. Kosonocky
- Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technologyby: Kouichi Nose, Takayasu Sakurai
- Reducing transitions on memory buses using sector-based encoding techniqueby: Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah
- Compilers for power and energy managementby: Ulrich Kremer
- Cooling and power consideration for semiconductors into the next centuryby: Christian Belady
- Enchanced multi-threshold (MTCMOS) circuits using variable well biasby: Stephen V. Kosonocky, Michael Immediato, Peter Cottrell, Terence Hook, Randy Mann, Jeff Brown
- Low power pipelining of linear systems: a common operand centric approachby: Daehong Kim, Dongwan Shin, Kiyoung Choi
- Effects of elevated temperature on tunable near-zero threshold CMOSby: Vjekoslav Svilan, James B. Burr, G. Tyler
- VTCMOS characteristics and its optimum conditions predicted by a compact analytical modelby: Hyunski Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai
- Cached-code compression for energy minimization in embedded processorsby: Luca Benini, Alberto Macii, Alberto Nannarelli
- Low-power technology mapping for mixed-swing logicby: Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone
- Energy efficient Modulation and MAC for Asymmetric RF Microsensor Systemsby: Andrew Wang, Seong-Hwan Cho, Charles Sodini, Anantha Chandrakasan
- Frequency-domain supply current macro-modelby: Srinivas Bodapati, Farid N. Najm
- Variable threshold CMOS (VTCMOS) in series connected circuitsby: Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai
- Run-time power estimation in high performance microprocessorsby: Russ Joseph, Margaret Martonosi
- Energy reduction in queues and stacks by adaptive bitwidth compressionby: Vasily G. Moshnyaga
- Design methodology and optimization strategy for dual-VTH scheme using commercially available toolsby: Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai
- Memory controller policies for DRAM power managementby: Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck
- Irredundant address bus encoding for low powerby: Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
- Scaling of stack effect and its application for leakage reductionby: Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar
- Modulation scaling for Energy Aware Communication Systemsby: Curt Schurgers, Olivier Aberthorne, Mani B. Srivastava
- Battery capacity measurement and analysis using lithium coin cell batteryby: Sung Park, Andreas Savvides, Mani B. Srivastava
- Automatic source code specialization for energy reductionby: Eui-Young Chung, Luca Benini, Giovanni De Micheli
- High density capacitance structures in submicron CMOS for low power RF applicationby: Tirdad Sowlati, Vickram Vathulya, Domine Leenaerts
- Low-energy for deep-submicron address busesby: Luca Macchiarulo, Enrico Macii, Massimo Poncino
- Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI designby: W. Chen, Wei Hwang, P. Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
- A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensorby: Kwang-Bo Cho, Alexander Krymski, Eric Fossum
- Hard real-time scheduling for low-energy using stochastic data and DVS processorsby: Flavius Gruian
- A 60dB, 246MHz CMOS variable gain amplifier for subsampling GSM receiversby: Mohamed Mostafa, Sherif Embabi, Mostafa Elmala
- Fast, flexible, cycle-accurate energy estimationby: Phillip Stanley-Marbell, Michael S. Hsiao
- Variable voltage task scheduling algorithms for minimizing energyby: Ali Manzak, Chaitali Chakrabarti
- Leakage current cancellation technique for low power switched-capacitor circuitsby: Louis S. Y. Wong, Shohan Hossain, Andre Walker
- A CMOS VCO architecture suitable for sub-1 volt high-frequency (8.7-10 GHz) RF applicationsby: Ahmed Mostafa, Mourad El-Gamal
- Low power address encoding using self-organizing listsby: Mahesh Mamidipaka, Dan Hirschberg, Nikil Dutt
- Estimation of power distribution in VLSI interconnectsby: Youngsoo Shin, Takayasu Sakurai
- Analysis and design of low-energy flip-flopsby: Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen
- Time-to-failure estimation for batteries in portable electronic systemsby: Daler N. Rakhmatov, Sarma B. K. Vrudhula
- A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPUby: Seiji Miura, Kazushige Ayukawa, Takao Watanabe
- A self-optimizing embedded microprocessor using a loop table for low powerby: Frank Vahid, Ann Gordon-Ross
- Theory and practical implementation of harmonic resonant rail driverby: Joong-Seok Moon, William C. Athas, Peter A. Beerel
- Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICsby: Ali Keshavarzi, S. Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De
- Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operationsby: Takeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura
- Analysis and implementation of charge recycling for deep sub-micron busesby: Paul-Peter Sotiriadis, Theodoros Konstantakopoulos, Anantha Chandrakasan
- L1 data cache decomposition for energy efficiencyby: Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
- A resonant clock generator for single-phase adiabatic systemsby: Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
- Wireless sensor networks: application driver for low power distributed systemsby: Deborah Estrin
- Energy priority scheduling for variable voltage processorsby: Johan Pouwelse, Koen Langendoen, Henk J. Sips
- Clocking strategies and scannable latches for low power appliacationsby: Victor V. Zyuban, D. Meltzer
- FV encoding for low-power data I/Oby: Jun Yang, Rajiv Gupta
- A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applicationsby: Dongkun Shin, Jihong Kim
- Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variationby: Hoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija
- Power-aware modulo scheduling for high-performance VLIW processorsby: Han-Saem Yun, Jihong Kim
- On the interaction of power distribution network with substrateby: Rajendran Panda, Savithri Sundareswaran, David Blaauw
- Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applicationsby: Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy
- Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessorsby: James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
- A system-level energy minimization approach using datapath width optimizationby: Yun Cao, Hiroto Yasuura
- Energy: efficient instruction dispatch buffer design for superscalar processorsby: Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge
- A sub-1V dual-threshold domino circuit using product-of-sum logicby: Koji Fujii, Takakuni Douseki, Yuichi Kado
- A low-leakage dynamic multi-ported register file in 0.13mm CMOSby: Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar
- Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceiversby: Lei Wang, Naresh R. Shanbhag
- Wireless beyond the third generation wireless beyond the third generation: facing the energy challengeby: Jan M. Rabaey
- Low-power direct-sequence spread-spectrum modem architecture for distributed wireless sensor networksby: Charles Chien, Igor Elgorriaga, Charles McConaghy
- Encodings for high-performance for energy-efficient signalingby: Alessandro Bogliolo
- Power-aware partitioned cache architecturesby: S. Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali
- Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit designby: Rongtian Zhang, Kaushik Roy, David Janes
- Maximum voltage variation in the power distribution network of VLSI circuits with RLC modelsby: Sudhakar Bobba, Ibrahim N. Hajj
- Energy efficient turbo decoding for 3G mobileby: David Garrett, Bing Xu, Chris Nicol
- Energy-efficient load and store reuseby: Jun Yang, Rajiv Gupta
- Dynamic voltage scheduling technique for low-power multimedia applications using buffersby: Chaeseok Im, Huiseok Kim, Soonhoi Ha
- Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessorsby: Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao
- Micro-operation cache: a power aware frontend for the variable instruction length ISAby: Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen
- Ultra-low power DLMS adaptive filter for hearing aid applicationsby: Hyung-il Kim, Kaushik Roy
- Compiler support for block bufferingby: Mahmut T. Kandemir, J. Ramanujam, Ugur Sezer
- 1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOSby: Song Ye, Koji Yano, C. Andre Salama
- Instruction flow-based front-end throttling for power-aware high-performance processorsby: Amirali Baniasadi, Andreas Moshovos
- Architecture strategies for energy-efficient packet forwarding in wireless sensor networksby: Vlasios Tsiatsis, Scott Zimbeck, Mani B. Srivastava
- A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous compandingby: Rola Baki, Mourad N. El-Gama
- Power reduction through work reuseby: Emil Talpes, Diana Marculescu
- Synthesis of low-leakage PD-SOI circuits with body-biasingby: Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
- A spatially-adaptive bus interface for low-switching communication (poster session)by: Andrea Acquaviva, Riccardo Scarsi
- Energy-efficient code generation for DSP56000 family (poster session)by: Sathishkumar Udayanarayanan, Chaitali Chakrabarti
- Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session)by: Andrea Gerosa, Arianna Novo, Andrea Neviani
- Analysis and design of low-phase-noise ring oscillatorsby: Liang Dai, Ramesh Harjani
- Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)by: Kanad Ghose
- Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOSby: Vjekoslav Svilan, Masataka Matsui, James B. Burr
- A micro-power mixed signal IC for battery-operated burglar alarm systemsby: Silvio Bolliri, Paolo Porcu, Luigi Raffo
- A low power unified cache architecture providing power and performance flexibility (poster session)by: Afzal Malik, Bill Moyer, Dan Cermak
- Optimization of high-performance superscalar architectures for energy efficiencyby: Victor V. Zyuban, Peter M. Kogge
- High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologiesby: Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
- Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)by: Koichi Nose, Soo-Ik Chae, Takayasu Sakurai
- Memory system energy (poster session): influence of hardware-software optimizationsby: G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
- "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session)by: Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
- Practical considerations of clock-powered logicby: William C. Athas
- Design of a low-power CMOS baseband circuit for wideband CDMA testbed (poster session)by: Chunlei Shi, Yue Wu, Mohammed Ismail
- Model and analysis for combined package and on-chip power grid simulationby: Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
- Achieving utility arbitrarily close to the optimal with limited energyby: Gang Qu, Miodrag Potkonjak
- High-level power estimation with interconnect effectsby: Kavel M. Büyüksahin, Farid N. Najm
- A three-port nRERL register file for ultra-low-energy applicationsby: Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae
- Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channelsby: Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara
- Design issues for dynamic voltage scalingby: Thomas D. Burd, Robert W. Brodersen
- A recursive algorithm for low-power memory partitioningby: Luca Benini, Alberto Macii, Massimo Poncino
- Low power self-timed Radix-2 division (poster session)by: Jae-Hee Won, Kiyoung Choi
- An asynchronous matrix-vector multiplier for discrete cosine transformby: Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong
- An adaptive on-chip voltage regulation technique for low-power applicationsby: Nicola Dragone, Akshay Aggarwal, L. Richard Carley
- Robust ultra-low power sub-threshold DTMOS logicby: Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
- Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS processby: Alain-Serge Porret, Thierry Melly, E. A. Vittoz, C. C. Enz
- Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)by: Naresh R. Shanbhag, K. Soumyanath, Samuel Martin
- Do our low-power tools have enough horse power? (panel session) (title only)by: Giovanni De Micheli, Tony Correale, Pietro Erratico, Srini Raghvendra, Hugo De Man, Jerry Frankil, Vivek Tiwari
- Energy efficient design of portable wireless systemsby: Tajana Simunic, Haris Vikalo, Peter W. Glynn, Giovanni De Micheli
- Bias boosting technique for a 1.9GHz class AB RF amplifierby: Tirdad Sowlati, Sifen Luo
- An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applicationsby: F. Svelto, S. Deantoni, G. Montagna, R. Castello
- Voltage scheduling in the IpARM microprocessor systemby: Trevor Pering, Thomas D. Burd, Robert W. Brodersen
- Low power DSP's for wireless communications (embedded tutorial session)by: Ingrid Verbauwhede, Chris Nicol
- MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environmentsby: Jason M. Musicer, Jan M. Rabaey
- Low-power considerations in the design of bluetooth (invited talk)by: Sven Mattisson
- A rate selection algorithm for quantized undithered dynamic supply voltage scaling (poster session)by: Lama H. Chandrasena, Michael J. Liebelt
- Low-power micromachined microsystems (invited talk)by: Khalil Najafi
- Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMIby: Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee
- Low power sequential circuit design by using priority encoding and clock gatingby: Xunwei Wu, Massoud Pedram
- Speeding up power estimation of embedded softwareby: Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan
- Power-optimal encoding for DRAM address bus (poster session)by: Wei-Chung Cheng, Massoud Pedram
- Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling (poster session)by: Sandeep Dhar, Dragan Maksimovic
- Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applicationsby: Erik Brockmeyer, Arnout Vandecappelle, Francky Catthoor
- Noise-aware power optimization for on-chip interconnectby: Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
- Power consumption reduction in high-speed Sigma-Delta bandpass modulatorsby: P. Cusinato, F. Stefani, A. Baschirotto
- Power minimization of functional units partially guarded computationby: Junghwan Choi, Jinhwan Jeon, Kiyoung Choi
- Profile-driven code execution for low power dissipation (poster session)by: Diana Marculescu
- A low-voltage CMOS multiplier for RF applications (poster session)by: Carl James Debono, Franco Maloberti, Joseph Micallef
- Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertionby: Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
- Operating-system directed power reductionby: Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
- Energy minimization with guaranteed quality of serviceby: Gang Qu, Miodrag Potkonjak
- New clock-gating techniques for low-power flip-flopsby: Antonio G. M. Strollo, E. Napoli, D. De Caro
- Low power synthesis of sum-of-products computation (poster session)by: Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
- A low-power clock and data recovery circuit for 2.5 Gb/s SDH receiversby: Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti
- Low power mixed analog-digital signal processingby: Mattias Duppils, Christer Svensson
- An improved pass transistor synthesis method for low power, high speed CMOS circuitsby: Tudor Vinereanu, Sverre Lidholm
- A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session)by: Friedel Gerfers, Yiannos Manoli
- Algorithmic transforms for efficient energy scalable computationby: Amit Sinha, Alice Wang, Anantha Chandrakasan
- Passive precharge and rippled power logic (PPRPL)by: Samuel B. Schaevitz, Christopher Lin
- Single-phase source-coupled adiabatic logicby: Suhwan Kim, Marios C. Papaefthymiou
- Circuit methods for the integration of low voltage (1.1-1.8V) analog functions on system-on-a-chip IC's in a single-poly CMOS processesby: Vladimir Koifman, Yachin Afek, Joseph Shor
- Algorithm and architecture of a 1V low power hearing instrument DSPby: Finn Müller, Nikolai Bisgaard, John Melanson
- Energy-efficient signal processing via algorithmic noise-toleranceby: Rajamohana Hegde, Naresh R. Shanbhag
- VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designsby: Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng
- Way-predicting set-associative cache for high performance and low energy consumptionby: Koji Inoue, Tohru Ishihara, Kazuaki Murakami
- CMOS front-end LNA-mixer of micropower RF wireless systemsby: Razieh Rofougaran, Tsung-Hsien Lin, William J. Kaiser
- Power scalable processing using distributed arithmeticby: Rajeevan Amirtharajah, Thucydides Xanthopoulos, Anantha Chandrakasan
- The impact of battery capacity and memory bandwidth on CPU speed-setting: a case studyby: Thomas L. Martin, Daniel P. Siewiorek
- Low power RF integrated circuits: principles and practiceby: A. A. Abidi, Houshang Darabi
- Comparison of class A amplifiers for low-power and low-voltage switched capacitor applicationsby: Christoph Schwoerer, Dominique Morche, Patrice Senn
- A completey on-chip voltage regulation technique for low power digital circuitsby: L. Richard Carley, Akshay Aggarwal
- Energy-efficient dynamic circuit design in the presence of crosstalk noiseby: Ganesh Balamurugan, Naresh R. Shanbhag
- Low power synthesis of dual threshold voltage CMOS VLSI circuitsby: Vijay Sundararajan, Keshab K. Parhi
- Energy-efficient design of battery-powered embedded systemsby: Tajana Simunic, Luca Benini, Giovanni De Micheli
- Dynamic power estimation using the probabilistic contribution measure (PCM)by: Hoon-Sang Jin, Myung-Soo Jang, Jin-Suk Song, Jin-Yong Lee, Taek-Soo Kim, Jeong-Taek Kong
- Instruction fetch energy reduction using loop caches for embedded applications with small tight loopsby: Lea Hwang Lee, Bill Moyer, John Arends
- Retractile clock-powered logicby: Nestoras Tzartzanis, William C. Athas
- Stochastic modeling of a power-managed system: construction and optimizationby: Qinru Qiu, Qing Wu, Massoud Pedram
- Non-stationary effects in trace-driven power analysisby: Radu Marculescu, Diana Marculescu, Massoud Pedram
- Efficient switching activity computation during high-level synthesis of control-dominated designsby: Alessandro Bogliolo, Luca Benini, Bruno Riccò, Giovanni De Micheli
- Global register allocation for minimizing energy consumptionby: Yumin Zhang, Xiaobo Hu, Danny Z. Chen
- Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codecby: Fuyuki Ichiba, Kojiro Suzuki, Shinji Mita, Tadahiro Kuroda, Tohru Furuyama
- Vibration-to-electric energy conversionby: Scott Meninger, Jose Oscar Mur-Miranda, Rajeevan Amirtharajah, Anantha Chandrakasan, Jeffrey Lang
- A 1.2V, 430MHz, 4dBm power amplifier and a 250muW front-end, using a standard digital CMOS processby: Thierry Melly, Alain-Serge Porret, C. C. Enz, M. Kayal, E. A. Vittoz
- Power macro-models for DSP blocks with application to high-level synthesisby: Subodh Gupta, Farid N. Najm
- Ultra-low power digital subthreshold logic circuitsby: Hendrawan Soeleman, Kaushik Roy
- A low energy architecture for fast PN acquisitionby: Christopher Deng, Charles Chien
- Challenges in clockgating for a low power ASIC methodologyby: David Garrett, Mircea R. Stan, Alvar Dean
- Databus charge recovery: practical considerationsby: Benjamin Bishop, Mary Jane Irwin
- Technology and design challenges for low power and high performanceby: Vivek De, Shekhar Borkar
- An architectural solution for the inductive noise problem due to clock-gatingby: Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
- Selective instruction compression for memory energy reduction in embedded systemsby: Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
- Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentationby: Kanad Ghose, Milind B. Kamble
- Energy efficient data transfer and storage organization for a MAP turbo decoder moduleby: Curt Schurgers, Francky Catthoor, Marc Engels
- The design of a low energy FPGAby: Varghese George, Hui Zhang, Jan M. Rabaey
- Circuit styles and strategies for CMOS VLSI design on SOIby: Fari Assaderaghi
- Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC'sby: Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
- Lower and upper bounds on the switching activity in scheduled data flow graphsby: Lars Kruse, Eike Schmidt, Gerd Jochens, Wolfgang Nebel
- Energy-per-cycle estimation at RTLby: Subodh Gupta, Farid N. Najm
- Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pumpby: Ayman ElSayed, Akbar Ali, Mohamed I. Elmasry
- An optimization technique for dual-output domino logicby: Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
- Clock distribution using multiple voltagesby: Jatuchai Pangjun, Sachin S. Sapatnekar
- Using dynamic cache management techniques to reduce energy in a high-performance processorby: Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
- Inverse polarity techniques for high-speed/low-power multipliersby: Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley
- Mixed-swing quadrail for low power dual-rail domino logicby: Bharath Ramasubramanian, Herman Schmit, L. Richard Carley
- Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltageby: Oliver Yuk-Hang Leung, Chung-Wai Yue, Chi-Ying Tsui, Roger S. Cheng
- Statistically optimized asynchronous barrel shifters for variable length codecsby: Peter A. Beerel, Sangyun Kim, Pei-Chuan Yeh, Kyeounsoo Kim
- Designing power efficient hypermedia processorsby: Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith
- Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuitsby: Ruchir Puri, Ching-Te Chuang
- Conforming inverted data store for low power memoryby: You-Sung Chang, Bong-Il Park, Chong-Min Kyung
- A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocellsby: Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka
- A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraintsby: Kostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, H. DeMan
- Modeling and automating selection of guarding techniques for datapath elementsby: William E. Dougherty, Donald E. Thomas
- System-level power optimization: techniques and toolsby: Luca Benini, Giovanni De Micheli
- Power-delay tradeoffs for radix-4 and radix-8 dividersby: Alberto Nannarelli, Tomás Lang
- Low power architecture of the soft-output Viterbi algorithmby: David Garrett, Mircea R. Stan
- Power dissipated by CMOS gates driving lossless transmission linesby: Yehea I. Ismail, Eby G. Friedman, José Luis Neves
- Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessorsby: Nikolaos Bellas, Ibrahim N. Hajj, George D.