Integration
2005
- An efficient architecture for lifting-based two-dimensional discrete wavelet transformsby: Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell v. 38 i. 3 p. 341 - 352
- Quality-of-service and error control techniques for mesh-based network-on-chip architecturesby: Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha v. 38 i. 3 p. 353 - 382
- High-speed systolic architectures for finite field inversionby: Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu v. 38 i. 3 p. 383 - 398
- Complete automatic Q tuning system on a chipby: Roghoyeh Salmeh, Brent Maundy v. 38 i. 3 p. 399 - 415
- Design and optimization of MOS current mode logic for parameter variationsby: Hassan Hassan, Mohab Anis, Mohamed I. Elmasry v. 38 i. 3 p. 417 - 437
- Equidistance routing in high-speed VLSI layout designby: Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi v. 38 i. 3 p. 439 - 449
- Detection probabilities of interconnect breaks: an analysisby: Shalini Ghosh, F. Joel Ferguson v. 38 i. 3 p. 451 - 465
- Logic-level mapping of high-level faultsby: Franco Fummi, Cristina Marconcini, Graziano Pravadelli v. 38 i. 3 p. 467 - 490
- Characterization of logic circuit techniques and optimization for high-leakage CMOS technologiesby: Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky v. 38 i. 3 p. 491 - 504
- Optimization of the VT?control method for low-power ultra-thin double-gate SOI logic circuitsby: Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khakifirooz, Ali Afzali-Kusha v. 38 i. 3 p. 505 - 513
- Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approachby: Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon v. 38 i. 3 p. 515 - 524
- A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADCby: Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald v. 38 i. 3 p. 525 - 540
- Automatic cell placement for quantum-dot cellular automataby: Ramprasad Ravichandran, Sung Kyu Lim, Michael T. Niemier v. 38 i. 3 p. 541 - 548
- Novel state minimization and state assignment in finite state machine design for low-power portable devicesby: Wen-Tsong Shiue v. 38 i. 4 p. 549 - 570
- Ringed bit-parallel systolic multipliers over a class of fields GF(2m)by: Yeun-Renn Ting, Erl-Huei Lu, Ya-Cheng Lu v. 38 i. 4 p. 571 - 578
- A simple built-in current sensor for IDDQ testing of CMOS data convertersby: Ashok K. Srivastava, Srinivas Rao Aluri, Anand Kumar Chamakura v. 38 i. 4 p. 579 - 596
- Multiplierless implementation of 2-D FIR filtersby: Arda Yurdakul v. 38 i. 4 p. 597 - 613
- Rail-to-rail constant-gm operational amplifier for video applicationsby: Juan M. Carrillo, J. Francisco Duque-Carrillo, José L. Ausín, Guido Torelli v. 37 i. 1 p. 1 - 16
- Challenges and directions for testing ICby: Liakot Ali, Roslina Sidek, Ishak Aris, Bambang Sunaryo Suparjo, Mohd. Alauddin Mohd. Ali v. 37 i. 1 p. 17 - 28
- A methodology for low power scheduling with resources operating at multiple voltagesby: Ashok Kumar, Magdy A. Bayoumi, Mohamed A. Elgamel v. 37 i. 1 p. 29 - 62
- A TCAD system for VLSI implementation of the CVD process using VHDLby: Georgios Ch. Sirakoulis v. 37 i. 1 p. 63 - 81
- Direct connect device core: design and applicationsby: Omar S. Elkeelany, Ghulam Chaudhry v. 37 i. 2 p. 83 - 102
- Efficient scalable VLSI architecture for Montgomery inversion in GF( p)by: Adnan Abdul-Aziz Gutub, Alexandre F. Tenca v. 37 i. 2 p. 103 - 120
- An evolutionary constraint satisfaction solution for over the cell channel routingby: Ahmet Ünveren, Adnan Acan v. 37 i. 2 p. 121 - 133
- Optimization of NULL convention self-timed circuitsby: Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, D. Ferguson, D. Lamb v. 37 i. 3 p. 135 - 165
- Low complexity bit-parallel systolic architecture for computing C+AB2 over a class of GF(2m)by: Yeun-Renn Ting, Erl-Huei Lu, Jau-Yien Lee v. 37 i. 3 p. 167 - 176
- Joint channel estimation and data detection under fading on reconfigurable fabricby: Sanjay Sharma, Sanjay Attri, R. C. Chauhan v. 37 i. 3 p. 177 - 189
- IP and design reuseby: Wolfgang Rosenstiel v. 37 i. 4 p. 191 - 192
- Safe integration of parameterized IPby: Vasco Jerinic, Dietmar Müller v. 37 i. 4 p. 193 - 221
- Strategies for the integration of hardware and software IP components in embedded systems-on-chipby: Flávio Rech Wagner, Wander O. Cesário, Luigi Carro, Ahmed Amine Jerraya v. 37 i. 4 p. 223 - 252
- Intelligent IP retrieval driven by application requirementsby: Martin Schaaf, Andrea Freßmann, Rainer Maximini, Ralph Bergmann, Alexander Tartakovski, Martin Radetzki v. 37 i. 4 p. 253 - 287
- Generic integration infrastructure for IP-based design processes and tools with a unified XML formatby: Markus Visarius, Johannes Lessmann, Frank Kelso, Wolfram Hardt v. 37 i. 4 p. 289 - 321
- Automation of IP qualification and IP exchangeby: Andreas Vörg, Wolfgang Rosenstiel v. 37 i. 4 p. 323 - 352
- Guest Editorialby: Luca Benini v. 38 i. 1 p. 1 - 2
- A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regimeby: Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen v. 38 i. 1 p. 3 - 17
- Cost considerations in network on chipby: Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny v. 38 i. 1 p. 19 - 42
- Self-timed communication platform for implementing high-performance systems-on-chipby: Pasi Liljeberg, Juha Plosila, Jouni Isoaho v. 38 i. 1 p. 43 - 67
- HERMES: an infrastructure for low area overhead packet-switching networks on chipby: Fernando Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost v. 38 i. 1 p. 69 - 93
- Issues in the development of a practical NoC: the Proteo conceptby: David A. Sigüenza-Tortosa, Tapani Ahonen, Jari Nurmi v. 38 i. 1 p. 95 - 105
- Run-time support for heterogeneous multitasking on reconfigurable SoCsby: Théodore Marescaux, Vincent Nollet, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Prabhat Avasare, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins v. 38 i. 1 p. 107 - 130
- Methods for evaluating and covering the design space during early design developmentby: Matthias Gries v. 38 i. 2 p. 131 - 183
- New approach to design for reusability of arithmetic cores in systems-on-chipby: Martin Margala, Hongfan Wang v. 38 i. 2 p. 185 - 203
- Optimum wire sizing of RLC interconnect with repeaters by: Magdy A. El-Moursy, Eby G. Friedman v. 38 i. 2 p. 205 - 225
- A programmable inductive position sensor interface circuitby: Falk Roewer, Ulrich Kleine, Klaus-Eberhard Salzwedel, Felix Mednikov, Chhrisitan Pfaffinger, Martin Sellen v. 38 i. 2 p. 227 - 243
- A clustering- and probability-based approach for time-multiplexed FPGA partitioningby: Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang v. 38 i. 2 p. 245 - 265
- On characterization of catastrophic faults in two-dimensional VLSI arraysby: Soumen Maity, Amiya Nayak, Bimal K. Roy v. 38 i. 2 p. 267 - 281
- Multithreshold voltage low-swing/low-voltage techniques in logic gatesby: Abdoul Rjoub, Odysseas G. Koufopavlou v. 38 i. 2 p. 283 - 298
- A hardware version of the RSA using the Montgomery's algorithm with systolic arraysby: Ali Ziya Alkar, Remziye Sönmez v. 38 i. 2 p. 299 - 307
- Application of the object-oriented principles for hardware and embedded system designby: Robertas Damasevicius, Vytautas Stuikys v. 38 i. 2 p. 309 - 339
- Hardware architectures for public key cryptographyby: Lejla Batina, Siddika Berna Örs, Bart Preneel, Joos Vandewalle v. 34 i. 1-2 p. 1 - 64
- Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysisby: Sheldon X.-D. Tan, C.-J. Richard Shi v. 34 i. 1-2 p. 65 - 86
- VLSI based fuzzy logic controller enabled adaptive interactive multiple model for target trackingby: Ramesh Chidambaram v. 35 i. 1 p. 1 - 10
- Systolic architectures for inversion/division using AB2 circuits in GF(2m)by: Nam-Yeun Kim, Kee-Young Yoo v. 35 i. 1 p. 11 - 24
- Pattern-based verification of connections to intellectual property coresby: Ilia Polian, Wolfgang Günther, Bernd Becker v. 35 i. 1 p. 25 - 44
- Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoderby: Dae Won Kim, Jun Rim Choi v. 35 i. 2 p. 47 - 67
- An efficient hierarchical timing-driven Steiner tree algorithm for global routingby: Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu v. 35 i. 2 p. 69 - 84
- Bit-serial architecture for rank order and stack filtersby: Ahmad Hiasat, Omar Hasan v. 36 i. 1-2 p. 3 - 12
- An arithmetic residue to binary conversion techniqueby: Ahmad A. Hiasat v. 36 i. 1-2 p. 13 - 25
- On minimum delay clustering without replicationby: Dimitri Kagaris v. 36 i. 1-2 p. 27 - 39
- Low-power VLSI synthesis of DSP systemsby: Sanjay Sharma, Sanjay Attri, R. C. Chauhan v. 36 i. 1-2 p. 41 - 54
- An improved circuit-partitioning algorithm based on min-cut equivalence relationby: Xianyang Jiang, Xubang Shen, Tianxu Zhang, Huayu Liu v. 36 i. 1-2 p. 55 - 68
- Generation of representative input vectors for parametric designs: from low precision to high precisionby: Shahar Bar-Or, Guy Even, Yariv Levin v. 36 i. 1-2 p. 69 - 82
- Adaptable I/O pad circuit for multiple voltage units bus operationby: J. A. Sainz, A. Rubio v. 36 i. 1-2 p. 83 - 86
- Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETSby: A. Srivastava, H. N. Venkata v. 36 i. 3 p. 87 - 101
- Synthesis of integer multipliers in sum of pseudoproducts formby: Valentina Ciriani, Fabrizio Luccio, Linda Pagli v. 36 i. 3 p. 103 - 119
- FPGA implementation of a near computation free image compression scheme based on adaptive decimationby: Angus Wu, Peter W. M. Tsang, Johnson Tang v. 36 i. 3 p. 121 - 143
- FPGA based multi-standard configurable FSK demodulatorby: Haytham Azmi, Hamed Elsimary, M. Ibrahim Youssef, Ahmad Safwat v. 36 i. 3 p. 145 - 154
- Erratum to "VLSI based fuzzy logic controller enabled adaptive interactive multiple model for target tracking" [Integration 35 (2003) 1-10]by: Ramesh Chidambaram, V. Sai Prithvi, V. Vaidehi v. 36 i. 3 p. 155 - 155
- Analog and mixed-signal IC design and design methodologiesby: Francisco V. Fernández v. 36 i. 4 p. 157 - 159
- 1-V quasi constant-gm input/output rail-to-rail CMOS op-ampby: Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín v. 36 i. 4 p. 161 - 174
- Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applicationsby: Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei v. 36 i. 4 p. 175 - 189
- Performance evaluation of the low-voltage CML D-latch topologyby: Massimo Alioto, Rosario Mita, Gaetano Palumbo v. 36 i. 4 p. 191 - 209
- Capacitor matching insensitive algorithmic ADC requiring no calibrationsby: Patrick Quinn, Maxim Pribytko v. 36 i. 4 p. 211 - 228
- A modem in CMOS technology for data communication on the low-voltage power lineby: O. Guerra, C. M. Domínguez-Matas, S. Escalera, J. M. García-González, Gustavo Liñán, R. del Río, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez v. 36 i. 4 p. 229 - 236
- IPRAIL - intellectual property reuse-based analog IC layout automationby: Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi v. 36 i. 4 p. 237 - 262
- A study about the efficiency of formal high-level synthesis applied to verificationby: José M. Mendías, Román Hermida, Olga Peñalba v. 31 i. 2 p. 101 - 131
- Cell selection from technology libraries for minimizing powerby: Yumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen v. 31 i. 2 p. 133 - 158
- Probability-driven routing in a datapath environmentby: Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert v. 31 i. 2 p. 159 - 182
- A new technique for IDDQ testing in nanometer technologiesby: Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni v. 31 i. 2 p. 183 - 194
- Shifts in INTEGRATION: 20 years of VLSI designby: Ralph H. J. M. Otten v. 32 i. 1-2 p. 1 - 4
- To Booth or not to Boothby: Wolfgang J. Paul, Peter-Michael Seidel v. 32 i. 1-2 p. 5 - 40
- Minimization of free BDDsby: Wolfgang Günther, Rolf Drechsler v. 32 i. 1-2 p. 41 - 59
- Verifying integrity of decision diagramsby: Rolf Drechsler v. 32 i. 1-2 p. 61 - 75
- Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL modelsby: Donald B. Shaw, Dhamin Al-Khalili, Come Rozon v. 32 i. 1-2 p. 77 - 97
- Systolic multiplier for Montgomery's algorithmby: Keon-Jik Lee, Kee-Young Yoo v. 32 i. 1-2 p. 99 - 109
- Chip design of MFCC extraction for speech recognitionby: Jia-Ching Wang, Jhing-Fa Wang, Yu-Sheng Weng v. 32 i. 1-2 p. 111 - 131
- A fuzzy search block-matching chip for motion estimationby: Pei-Yin Chen v. 32 i. 1-2 p. 133 - 147
- Editorialby: Georges G. E. Gielen v. 33 i. 1-2 p. 1 - 2
- Bit-level two's complement matrix multiplicationby: Radhika S. Grover, Weijia Shang, Qiang Li v. 33 i. 1-2 p. 3 - 21
- FAST: FFT ASIC automated synthesisby: Luca Fanucci, Massimiliano Forliti, Pierangelo Terreni v. 33 i. 1-2 p. 23 - 37
- Minimization of Word-Level Decision Diagramsby: Rolf Drechsler, Wolfgang Günther, Stefan Höreth v. 33 i. 1-2 p. 39 - 70
- A protocol converter for nonblocking protocolsby: Young Moo Lee, Kyu Ho Park v. 33 i. 1-2 p. 71 - 88
- A reversible carry-look-ahead adder using control gatesby: Bart Desoete, Alexis De Vos v. 33 i. 1-2 p. 89 - 104
- Delay-insensitive gate-level pipeliningby: Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson v. 30 i. 2 p. 103 - 131
- Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrateby: Hasan Ymeri, Bart Nauwelaers, Karen Maex v. 30 i. 2 p. 133 - 141
- Network flow based buffer planningby: Xiaoping Tang, D. F. Wong v. 30 i. 2 p. 143 - 155
- Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional linksby: Soumen Maity, Bimal K. Roy, Amiya Nayak v. 30 i. 2 p. 157 - 168
- A bit-interleaved systolic architecture for a high-speed RSA systemby: Kiamal Z. Pekmestzi, Nikos K. Moshopoulos v. 30 i. 2 p. 169 - 175
- A survey on multi-net global routing for integrated circuitsby: Jiang Hu, Sachin S. Sapatnekar v. 31 i. 1 p. 1 - 49
- History-based dynamic BDD minimizationby: Rolf Drechsler, Wolfgang Günther v. 31 i. 1 p. 51 - 63
- Floorplanning with abutment constraints based on corner block listby: Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu v. 31 i. 1 p. 65 - 77
- A parametric VLSI architecture for video motion estimationby: Luca Fanucci, Sergio Saponara, Lorenzo Bertini v. 31 i. 1 p. 79 - 100
- OKFDD minimization by genetic algorithms with application to circuit designby: Rolf Drechsler, Bernd Becker, Nicole Drechsler v. 28 i. 2 p. 121 - 139
- Bounds, designs and layouts for multi-terminal FPIC architecturesby: Dinesh Bhatia, James Haralambides v. 28 i. 2 p. 141 - 156
- A GA with heuristic-based decoder for IC floorplanningby: B. H. Gwee, M. H. Lim v. 28 i. 2 p. 157 - 172
- A hardware implementation of realloc functionby: Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang v. 28 i. 2 p. 173 - 184
- A parallel VLSI architecture of Kalman-filter-based algorithms for signal reconstructionby: Daniel Massicotte v. 28 i. 2 p. 185 - 196
- Performance planningby: Ralph H. J. M. Otten, Robert K. Brayton v. 29 i. 1 p. 1 - 24
- Integration of retiming with architectural floorplanningby: Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton v. 29 i. 1 p. 25 - 43
- Technology mapping for area and speedby: Dirk-Jan Jongeneel, Ralph H. J. M. Otten v. 29 i. 1 p. 45 - 66
- Combinatorial cell design for CMOS librariesby: Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok v. 29 i. 1 p. 67 - 93
- Boolean function representation and spectral characterization using AND/OR graphsby: A. Zuzek, Rolf Drechsler, Mitchell A. Thornton v. 29 i. 2 p. 101 - 116
- An accurate model for the transient simulation of lossy interconnects based on a novel discretization formulaby: Hans Georg Brachtendorf, Rainer Laur v. 29 i. 2 p. 117 - 129
- Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnectionsby: Kevin T. Tang, Eby G. Friedman v. 29 i. 2 p. 131 - 165
- A dual precision IEEE floating-point multiplierby: Guy Even, Silvia M. Mueller, Peter-Michael Seidel v. 29 i. 2 p. 167 - 180
- VLSI design of 1-D DWT architecture with parallel filtersby: Chokri Souani, Mohamed Abid, Kholdoun Torki, Rached Tourki v. 29 i. 2 p. 181 - 207
- A fast hypergraph min-cut algorithm for circuit partitioningby: Wai-Kei Mak, D. F. Wong v. 30 i. 1 p. 1 - 11
- Redundant arithmetic, algorithms and implementationsby: Alejandro F. González, Pinaki Mazumder v. 30 i. 1 p. 13 - 53
- Computation of capacitance matrix for integrated circuit interconnects using semi-analytic Green's function methodby: Hasan Ymeri, Bart Nauwelaers, Karen Maex v. 30 i. 1 p. 55 - 63
- Test-set partitioning for multi-weighted random LFSRsby: Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar v. 30 i. 1 p. 65 - 75
- An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitionsby: Dominique Lavenier v. 30 i. 1 p. 77 - 89
- Management of charge pump circuitsby: G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni v. 30 i. 1 p. 91 - 101
- Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1by: S. Ramanathan, V. Visvanathan v. 27 i. 1 p. 1 - 32
- Establishing latch correspondence for sequential circuits using distinguishing signaturesby: Janett Mohnke, Paul Molitor, Sharad Malik v. 27 i. 1 p. 33 - 46
- Provably good moat routingby: Joseph L. Ganley, James P. Cohoon v. 27 i. 1 p. 47 - 56
- A timing-driven floorplanning algorithm with the Elmore delay model for building block layoutby: Tetsushi Koide, Shin'ichi Wakabayashi v. 27 i. 1 p. 57 - 76
- Maximum weighted independent sets on transitive graphs and applications1by: Dimitri Kagaris, Spyros Tragoudas v. 27 i. 1 p. 77 - 86
- Multi-schedule design space exploration: an alternative synthesis frameworkby: Mehmet Emin Dalkiliç, Vijay Pitchumani v. 27 i. 2 p. 87 - 112
- Generating new benchmark designs using a multi-terminal net modelby: Dirk Stroobandt, Jo Depreitere, Jan Van Campenhout v. 27 i. 2 p. 113 - 129
- Timing driven cell replication during placement for cycle time optimizationby: Ingmar Neumann, Hans-Ulrich Post v. 27 i. 2 p. 131 - 141
- Synthesis of low-power CMOS circuits using hybrid topologiesby: Michael Gallant, Dhamin Al-Khalili v. 27 i. 2 p. 143 - 163
- Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitanceby: Youxin Gao, D. F. Wong v. 27 i. 2 p. 165 - 178
- Assessing merged DRAM/Logic technologyby: Ytong-Bin Kim, Tom W. Chen v. 27 i. 2 p. 179 - 194
- High-speed redundant reciprocal approximationby: Peter-Michael Seidel v. 28 i. 1 p. 1 - 12
- Synthesis of ASIPs for DSP algorithmsby: S. Ramanathan, V. Visvanathan, S. K. Nandy v. 28 i. 1 p. 13 - 32
- Retiming control logicby: Naresh Maheshwari, Sachin S. Sapatnekar v. 28 i. 1 p. 33 - 53
- Unified data path allocation and BIST intrusionby: Katzalin Olcoz, Francisco Tirado, Hortensia Mecha v. 28 i. 1 p. 55 - 99
- New efficient totally self-checking Berger code checkersby: Xrysovalantis Kavousianos, Nikolos Nikolos, G. Foukarakis, T. Gnardellis v. 28 i. 1 p. 101 - 118
- VLSI design in the 3rd dimensionby: Stephen Strickland, Erhan Ergin, David R. Kaeli, Paul M. Zavracky v. 25 i. 1 p. 1 - 16
- Theoretical properties of LFSRs for built-in self testby: Christian Dufaza v. 25 i. 1 p. 17 - 35
- Accurate and efficient power simulation strategy by compacting the input vector setby: Chi-Ying Tsui, Massoud Pedram v. 25 i. 1 p. 37 - 52
- Systolic-based parallel architecture for the longest common subsequences problemby: Guillaume Luce, Jean Frédéric Myoupo v. 25 i. 1 p. 53 - 70
- An algorithm for finding a non-trivial lower bound for channel routing1by: Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal v. 25 i. 1 p. 71 - 84
- An approximation algorithm for the register allocation problemby: Klaus Jansen, Joachim Reiter v. 25 i. 2 p. 89 - 102
- Comparison of the VLSI cost/performance properties of two Reed-Solomon decoding algorithms1by: Sylvia M. Jennings, Joep L. W. Kessels v. 25 i. 2 p. 103 - 110
- GreyHound: A methodology for utilizing datapath regularity in standard design flowsby: R. X. T. Nijssen, C. A. J. van Eijk v. 25 i. 2 p. 111 - 135
- On the optimal four-way switch box routing structures of FPGA greedy routing architectures1by: Jiaofeng Pan, Yu-Liang Wu, C. K. Wong, Guiying Yan v. 25 i. 2 p. 137 - 159
- High-level synthesis techniques for functional test pattern execution1by: Inki Hong, Darko Kirovski, Kevin Kornegay, Miodrag Potkonjak v. 25 i. 2 p. 161 - 180
- Testing with decision diagramsby: Bernd Becker v. 26 i. 1-2 p. 5 - 20
- Delay fault models for VLSI circuits1by: Irith Pomeranz, Sudhakar M. Reddy v. 26 i. 1-2 p. 21 - 40
- Sequential test generators: past, present and futureby: Yong Chang Kim, Kewal K. Saluja v. 26 i. 1-2 p. 41 - 54
- BIST for systems-on-a-chipby: Hans-Joachim Wunderlich v. 26 i. 1-2 p. 55 - 78
- High-level test synthesis: a surveyby: Indradeep Ghosh, Niraj K. Jha v. 26 i. 1-2 p. 79 - 99
- An approach to test synthesis from higher levelby: Michiko Inoue, Hideo Fujiwara v. 26 i. 1-2 p. 101 - 116
- FTROM: A Silicon Compiler for Fault-tolerant ROMsby: Anurag Gupta, Kanad Chakraborty, Pinaki Mazumder v. 26 i. 1-2 p. 117 - 140
- Design of mixed-signal systems for testabilityby: Vishwani D. Agrawal v. 26 i. 1-2 p. 141 - 150
- Mixed-signal on-chip timing measurementsby: Mani Soma v. 26 i. 1-2 p. 151 - 165
- IDDQ testing: state of the art and future trendsby: Antoni Ferré, Eugeni Isern, J. Rius, R. Rodríguez-Montañés, Joan Figueras v. 26 i. 1-2 p. 167 - 196
- On-line testing for VLSI: state of the art and trendsby: Michael Nicolaidis v. 26 i. 1-2 p. 197 - 209
- A new approach in feature interaction testingby: Masahide Nakamura, Tohru Kikuno v. 26 i. 1-2 p. 211 - 223
- Retiming: Theory and practiceby: Narendra V. Shenoy v. 22 i. 1-2 p. 1 - 21
- A real-time systolic integer multiplierby: Guy Even v. 22 i. 1-2 p. 23 - 38
- Implementing and clustering modules with complex delaysby: Spyros Tragoudas, Dimitrios Karayiannis v. 22 i. 1-2 p. 39 - 57
- Fast analytical approximations of the transient response of coupled lossy interconnects in VLSI circuits with frequency-dependent parameters for higher hierarchical simulation levelsby: Lohit S. Dutta, Thomas-M. Winkel v. 22 i. 1-2 p. 59 - 85
- A new modeling technique for mixed-mode simulation of CMOS circuitsby: Ganesh Samudra, Lee Teng Kiat v. 22 i. 1-2 p. 87 - 99
- A modified noising algorithm for the graph partitioning problemby: V. Sudhakar, C. Siva Ram Murthy v. 22 i. 1-2 p. 101 - 113
- Signal compression through spatial frequency-based motion estimationby: Vinod Menezes, S. K. Nandy, Biswadip Mitra v. 22 i. 1-2 p. 115 - 135
- Constructing minimal spanning/Steiner trees with bounded path lengthby: Jaewon Oh, Iksoo Pyo, Massoud Pedram v. 22 i. 1-2 p. 137 - 163
- A note on architectures for large-capacity CAMsby: Behrooz Parhami v. 22 i. 1-2 p. 165 - 171
- Authors' reply to "A note on architectures for large-capacity CAMs"by: Kenneth J. Schultz, P. Glenn Gulak v. 22 i. 1-2 p. 173 - 176
- A unified approach for scheduling and allocationby: R. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha v. 23 i. 1 p. 1 - 35
- Scheduling with multiple voltagesby: Salil Raje, Majid Sarrafzadeh v. 23 i. 1 p. 37 - 59
- How good are slicing floorplans?by: F. Y. Young, D. F. Wong v. 23 i. 1 p. 61 - 73
- A complete testing strategy based on interacting and hierarchical FSMsby: Franco Fummi, Donatella Sciuto v. 23 i. 1 p. 75 - 93
- An embedded CDMA-receiver A design exampleby: Jack P. F. Glas v. 23 i. 1 p. 95 - 111
- Mirroring: a technique for pipelining semi-systolic and systolic arraysby: Michael Braun, Guy Even, Thomas Walle v. 23 i. 2 p. 115 - 130
- A BDD-based verification method for large synthesized circuitsby: C. A. J. van Eijk v. 23 i. 2 p. 131 - 149
- Accuracy and fidelity of fast net length estimatesby: Joseph L. Ganley v. 23 i. 2 p. 151 - 155
- Serial diagnostic fault simulation for synchronous sequential circuitsby: Shung-Chih Chen, Jer-Min Jou v. 23 i. 2 p. 157 - 170
- Content-addressable memory core cells A surveyby: Kenneth J. Schultz v. 23 i. 2 p. 171 - 188
- A new approach for the design of linear systolic arrays for computing third-order cumulantsby: Mohammed A. Aloqeely, Mohammed A. Al-Turaigi, Saleh A. Alshebeili v. 24 i. 1 p. 1 - 17
- RTL verification of timed asynchronous and heterogeneous systems using symbolic model checkingby: Vida Vakilotojar, Peter A. Beerel v. 24 i. 1 p. 19 - 35
- A non-iterative gate resizing algorithm for high reduction in power consumptionby: Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac v. 24 i. 1 p. 37 - 52
- A timing-driven placement algorithm with the Elmore delay model for row-based VLSIsby: Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida v. 24 i. 1 p. 53 - 77
- VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirementsby: An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin v. 24 i. 1 p. 79 - 97
- State assignment based on two-dimensional placement and hypercube mappingby: Shihming Liu, Massoud Pedram, Alvin M. Despain v. 24 i. 2 p. 101 - 118
- Overcoming chip-to-chip delays and clock skewsby: Guy Even, Ami Litman v. 24 i. 2 p. 119 - 133
- On retiming for FPGA logic module minimizationby: Y. P. Chen, D. F. Wong v. 24 i. 2 p. 135 - 145
- A graph theoretic approach to feed-through pin assignmentby: Y. P. Chen, D. F. Wong v. 24 i. 2 p. 147 - 158
- Modeling and designing silicon thin-film inductors and transformers using HSPICE for RFIC applicationsby: A. Valkodai, T. Manku v. 24 i. 2 p. 159 - 171
- Performance optimization of VLSI interconnect layoutby: Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden v. 21 i. 1-2 p. 1 - 94
- Built-in self-test for folded bit-line Mbit DRAMsby: Emil Gizdarski v. 21 i. 1-2 p. 95 - 112
- Synthesis of systems specified as interacting VHDL processesby: Petru Eles, Krzysztof Kuchcinski, Zebo Peng v. 21 i. 1-2 p. 113 - 138
- Modelling, analysis and synthesis of asynchronous control circuits using Petri netsby: Alexandre Yakovlev, Albert Koelmans, Alexei L. Semenov, D. J. Kinniment v. 21 i. 3 p. 143 - 170
- A three-layer over-the-cell multi-channel router for a new cell modelby: Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida v. 21 i. 3 p. 171 - 189
- Assignment and allocation of highly testable data paths under scan optimizationby: Asad A. Ismaeel, M. K. Dhodhi, Rajan Mathew v. 21 i. 3 p. 191 - 207
- Testing CMOS combinational iterative logic arrays for realistic faultsby: Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis v. 21 i. 3 p. 209 - 228
- On programming VLSI concurrent array processorsby: Armin B. Cremers v. 2 p. 15 - 26
![[SWISH++]](/docis/swish-powered.gif){kind=small}
